Massive Multiple-Input Multiple-Output (MIMO) communication systems are being investigated intensively for positioning services. Enhancing the accuracy on these services in terms of accurate positioning of users is an important goal to improve related applications in the future. Convolutional Neural Networks (CNNs) has been proposed to infer the position of a user from Channel State Information (CSI) of a massive MIMO system. This paper investigates different architectures of CNNs to enhance the accuracy of a fingerprint-based positionina system. Three new CNNs has been proposed in which the Convolutional Layer (CL) and the Fully Connected (FC) layer are re-dimensioned. Batch Normalization (BN) layer is introduced to the layer structure of the newly proposed CNNs. The CNNs were trained, and accordingly mean error is measured. The first re-constructed CNN composed of 13 CLs, 7 BNs, and 3 FC layers has achieved the best accuracy out of the three models. It managed to achieve a mean error of 10.09 mm, that outperforms a similar work by 82 % in terms of positioning accuracy. Pruning was added to the layer structure of the newly proposed CNN s. It reduced the model size significantly, approximately by 65 % compared to a similar model of previous work.

The acceleration of Deep Neural Networks (DNNs) has attracted much attention in research. Many critical real-time applications benefit from DNN accelerators but are limited by their compute-intensive nature. This work introduces an accelerator for Convolutional Neural Network (CNN), based on a hybrid optoelectronic computing architecture and residue number system (RNS). The RNS reduces the optical critical path and lowers the power requirements. In addition, the wavelength division multiplexing (WDM) allows high-speed operation at the system level by enabling high-level parallelism. The proposed RNS compute modules use one-hot encoding, and thus enable fast switching between the electrical and optical domains. We propose a new architecture that combines residue electrical adders and optical multipliers as the matrix-vector multiplication unit. Moreover, we enhance the implementation of different CNN computational kernels using WDM-enabled RNS based integrated photonics. The area and power efficiency of the proposed accelerator are 0.39 TOPS/s/mm(2) and 3.22 TOPS/s/W, respectively. In terms of computation capability, the proposed chip is 12.7x and 4.02x better than other optical implementation and memristor implementation, respectively. Our experimental evaluation using DNN benchmarks illustrates that our architecture can perform on average more than 72 times faster than GPU under the same power budget. © 2023 ACM, Inc.

The privacy aspect of state estimation algorithms has been drawing high research attention due to the necessity for a trustworthy private environment in cyber-physical systems. These systems usually engage cloud-computing platforms to aggregate essential information from spatially distributed nodes and produce desired estimates. The exchange of sensitive data among semi-honest parties raises privacy concerns, especially when there are coalitions between parties. We propose two privacy-preserving protocols using Kalman filter and partially homomorphic encryption of the measurements and estimates while exposing the covariances and other model parameters. We prove that the proposed protocols achieve satisfying computational privacy guarantees against various coalitions based on formal cryptographic definitions of indistinguishability. We evaluate the proposed protocols to demonstrate their efficiency using data from a real testbed. © 2022 EUCA.

The Internet-of-Things has given rise to an over-whelming number of resource-constrained devices which must communicate securely with a core server. Due to the variability in processing power among these devices, one lightweight crypto-graphic (LWC) algorithm cannot be standardized. This creates a problem for fog and cloud architectures, where a central server, is subsequently required to support many ciphers. Compounding this problem, LWC ciphers tend to require large numbers of rounds to achieve high security levels, thus occupying the server for unacceptable lengths of time. To minimize LWC overhead, we propose a novel parallel mapping of LWC ciphers and ReCPE, a reconfigurable, lightweight processing element (PE) for use in hardware security modules (HSM) and array processors such as smartNICs. The proposed design was synthesized for both FPGA and ASIC implementations. We validate the ReCPE architecture by comparing it with a baseline array processor and custom field programmable gate array (FPGA) LWC accelerators that use dynamic reconfiguration. The ReCPE architecture is shown to accelerate cryptographic processing by 2× when compared to a baseline PE, with 30% and 60% increases in logic and registers, respectively. Furthermore, we achieve a 50× improvement in dynamic reconfiguration environments when compared to custom FPGA accelerators. ©2021 IEEE

Deep Neural Networks (DNNs) are currently used in many fields, including critical real-time applications. Due to its compute-intensive nature, speeding up DNNs has become an important topic in current research. We propose a hybrid opto-electronic computing architecture targeting the acceleration of DNNs based on the residue number system (RNS). In this novel architecture, we combine the use of Wavelength Division Multiplexing (WDM) and RNS for efficient execution. WDM is used to enable a high level of parallelism while reducing the number of optical components needed to decrease the area of the accelerator. Moreover, RNS is used to generate optical components with short optical critical paths. In addition to speed, this has the advantage of lowering the optical losses and reducing the need for high laser power. Our RNS compute modules use one-hot encoding and thus enable fast switching between the electrical and optical domains. 

In this work, we demonstrate how to implement the different DNN computational kernels using WDM-enabled RNS based integrated photonics. We provide an accelerator architecture that uses our designed components and perform design space exploration to select efficient architecture parameters. Compared to memristor crossbars, our residue matrix-vector multiplication unit has two orders of magnitude higher peak performance. Our experimental evaluation using DNN benchmarks illustrates that our architecture can perform more than 19 times faster than the state of the art GPUs under the same power budget. © 2020 ACM.

A content addressable memory (CAM) is a type of memory that implements a parallel search engine at its core. A CAM takes as an input a value and outputs the address where this value is stored in case of a match. CAMs are used in a wide range of applications including networking, cashing, neuromorphic associative memories, multimedia, and data analytics. Here, we introduce a novel opto-electronic CAM (OE-CAM) utilizing the integrated silicon photonic platform. In our approach, we explore the performance of an experimental OE-CAM and verify the efficiency of the device at 25 Gbit/s while maintaining the bit integrity under noise conditions. We show that OE-CAM enables a) two orders of magnitude faster search functionality resulting in b) a five orders of magnitude lower power-delay-product compared to CAMs implementations based on other emerging technologies. This remarkable performance potential is achieved by utilizing i) a high parallelism of wavelength-division-multiplexing in the optical domain, combined with ii) 10's of GHz-fast opto-electronic components, packaged in iii) integrated photonics for 10-100's ps-short communication delays. We further verify the upper optical input power limit of this OE-CAM to be given by parasitic nonlinearities inside the silicon waveguides, and the minimal detectable optical power at the back-end photoreceiver's responsivity given channel noise. Such energy-efficient and short-delay OE-CAMs could become a key component of functional photonic-augmented ASICS, co-processors, or smart sensors. © IEEE

Due to the end of Moore’s law and Dennard scaling, we are entering a new era of processors. Computing systems are increasingly facing power and performance challenges due to both device- and circuit-related challenges with resistive and capacitive charging. Non-von Neumann architectures are needed to support future computations through innovative post-Moore’s law architectures. To enable these emerging architectures with high-performance and at ultra-low power, both parallel computation and inter-node communication on-the-chip can be supported using photons. To this end, we introduce ROC, a reconfigurable optical computer that can solve partial differential equations (PDEs). PDE solvers form the basis for many traditional simulation problems in science and engineering that are currently performed on supercomputers. Instead of solving problems iteratively, the proposed engine uses a resistive mesh architecture to solve a PDE in a single iteration (one-shot). Instead of using actual electrical circuits, the physical underlying hardware emulates such structures using a silicon-photonics mesh that splits light into separate pathways, allowing it to add or subtract optical power analogous to programmable resistors. The time to obtain the PDE solution then only depends on the time-of-flight of a photon through the programmed mesh, which can be on the order of 10’s of picoseconds given the millimeter-compact integrated photonic circuit. Numerically validated experimental results show that, over multiple configurations, ROC can achieve several orders of magnitude improvement over state-of-the-art GPUs when speed, power, and size are taken into account. Further, it comes within approximately 90% precision of current numerical solvers. As such, ROC can be a viable reconfigurable, approximate computer with the potential for more precise results when replacing silicon-photonics building blocks with nanoscale photonic lumped-elements. © 2020 ACM