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Weckstén, Mattias
Alternative names
Publications (10 of 13) Show all publications
Vaske, C., Weckstén, M. & Järpe, E. (2017). Velody — A novel method for music steganography. In: 2017 3rd International Conference on Frontiers of Signal Processing (ICFSP 2017): September 6-8, 2017, Paris, France. Paper presented at 2017 3rd International Conference on Frontiers of Signal Processing (ICFSP 2017), Paris, France, September 6-8, 2017 (pp. 15-19). Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>Velody — A novel method for music steganography
2017 (English)In: 2017 3rd International Conference on Frontiers of Signal Processing (ICFSP 2017): September 6-8, 2017, Paris, France, Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 15-19Conference paper, Published paper (Refereed)
Abstract [en]

This study describes a new method for musical steganography utilizing the MIDI format. MIDI is a standard music technology protocol that is used around the world to create music and make it available for listening. Since no publicly available method for MIDI steganography has been found (even though there are a few methods described in the literature), the study investigates how a new algorithm for MIDI steganography can be designed so that it satisfies capacity and security criteria. As part of the study, a method for using velocity values to hide information in music has been designed and evaluated, during which the capacity of the method is found to be comparable with similar methods. In an audibility test, it is observed that audible impact on the music can not be distinguished at any reasonable significance level, which means that also a security criterion is met. © 2017 IEEE.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2017
Keywords
Algorithms, Security of data, Security systems, Steganography, Velocity, audibility, capacity, Embeddings, Information hiding technology, MIDI, music, Secret messages, teganography, Signal processing
National Category
Media and Communication Technology
Identifiers
urn:nbn:se:hh:diva-40213 (URN)10.1109/ICFSP.2017.8097052 (DOI)000425242400003 ()2-s2.0-85039897034 (Scopus ID)978-1-5386-1038-1 (ISBN)978-1-5386-1037-4 (ISBN)978-1-5386-1036-7 (ISBN)978-1-5386-1039-8 (ISBN)
Conference
2017 3rd International Conference on Frontiers of Signal Processing (ICFSP 2017), Paris, France, September 6-8, 2017
Available from: 2019-10-28 Created: 2019-10-28 Last updated: 2019-10-28
Weckstén, M., Frick, J., Sjostrom, A. & Järpe, E. (2016). A Novel Method for Recovery from Crypto Ransomware Infections. In: 2016 2nd IEEE International Conference on Computer and Communications, ICCC 2016 - Proceedings: . Paper presented at 2nd IEEE International Conference on Computer and Communications (ICCC), Oct 14-17, 2016, Chengdu, China (pp. 1354-1358). New York: IEEE
Open this publication in new window or tab >>A Novel Method for Recovery from Crypto Ransomware Infections
2016 (English)In: 2016 2nd IEEE International Conference on Computer and Communications, ICCC 2016 - Proceedings, New York: IEEE, 2016, p. 1354-1358Conference paper, Published paper (Refereed)
Abstract [en]

Extortion using digital platforms is an increasing form of crime. A commonly seen problem is extortion in the form of an infection of a Crypto Ransomware that encrypts the files of the target and demands a ransom to recover the locked data. By analyzing the four most common Crypto Ransomwares, at writing, a clear vulnerability is identified; all infections rely on tools available on the target system to be able to prevent a simple recovery after the attack has been detected. By renaming the system tool that handles shadow copies it is possible to recover from infections from all four of the most common Crypto Ransomwares. The solution is packaged in a single, easy to use script. © 2016 IEEE.

Place, publisher, year, edition, pages
New York: IEEE, 2016
Series
IEEE International Conference on Computer Communications and Networks, ISSN 1095-2055
Keywords
component, crypto ransom ware, malware, recovery, extortion, network security
National Category
Embedded Systems
Identifiers
urn:nbn:se:hh:diva-35642 (URN)10.1109/CompComm.2016.7924925 (DOI)000411576802046 ()2-s2.0-85020228603 (Scopus ID)978-1-4673-9026-2 (ISBN)
Conference
2nd IEEE International Conference on Computer and Communications (ICCC), Oct 14-17, 2016, Chengdu, China
Available from: 2017-12-07 Created: 2017-12-07 Last updated: 2018-08-28Bibliographically approved
Wecksten, M. & Jonsson, M. (2008). Less pessimistic worst-case delay analysis for packet-switched networks. In: IEEE International Conference on Emerging Technologies and Factory Automation, 2008. ETFA 2008. Paper presented at 13th IEEE International Conference on Emerging Technologies and Factory Automation, Hamburg, GERMANY, SEP 15-18, 2008 (pp. 1213-1219). Piscataway, N.J.: IEEE Press
Open this publication in new window or tab >>Less pessimistic worst-case delay analysis for packet-switched networks
2008 (English)In: IEEE International Conference on Emerging Technologies and Factory Automation, 2008. ETFA 2008, Piscataway, N.J.: IEEE Press, 2008, p. 1213-1219Conference paper, Published paper (Refereed)
Abstract [en]

The rapid growth of distributed real-time systems creates a need for cheap and available network solutions while still fulfilling the real-time requirements. In this paper we propose a method for less pessimistic delay analysis for packet switched first come first serve network, when knowing the intervals of possible message generation. Experiments show that the proposed method generates the expected results according to theoretical limitations of the experiment cases. The experiments also show that the proposed method could be practically used for non-trivial systems. Suggestions are given for future work on how to relax traffic requirements and how to cope with circular dependencies.

Place, publisher, year, edition, pages
Piscataway, N.J.: IEEE Press, 2008
Series
IEEE International Conference on Emerging Technologies and Factory Automation-ETFA, ISSN 1946-0740
Keywords
packet switching, telecommunication traffic
National Category
Engineering and Technology
Identifiers
urn:nbn:se:hh:diva-2139 (URN)10.1109/ETFA.2008.4638556 (DOI)000260495500198 ()2-s2.0-56349156068 (Scopus ID)2082/2534 (Local ID)978-1-4244-1505-2 (ISBN)2082/2534 (Archive number)2082/2534 (OAI)
Conference
13th IEEE International Conference on Emerging Technologies and Factory Automation, Hamburg, GERMANY, SEP 15-18, 2008
Note

©2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

Available from: 2008-11-13 Created: 2008-11-13 Last updated: 2018-03-23Bibliographically approved
Wecksten, M. (2008). RealLife - en tekniköversikt. Halmstad: Högskolan i Halmstad
Open this publication in new window or tab >>RealLife - en tekniköversikt
2008 (Swedish)Report (Other academic)
Abstract [sv]

RealLife är en sammankopplink mellan användarens plattform och tjänsteleverantörer via en central databas. Tanken är att en individidentifierare, UBI passport, ska vara kärnan i systemet som möjliggör att flytta innehåll från plattform till plattform. Genom att ta kontroll över den databas som samlar allt material och alla tjänster får man möjlighet att sälja extremfokuserad reklam. All den teknik som krävs för att genomföra projektet RealLife finns tillgänglig i någon form redan idag. Avgörande blir om man lyckas att göra så att användaren känner någon nytta utöver vad man skulle ha fått från en traditionell söktjänst. Detta kräver articifiell intelligens utöver vad som är tillgängligt idag.

Place, publisher, year, edition, pages
Halmstad: Högskolan i Halmstad, 2008. p. 14
Series
IDE ; 0853
Keywords
Ubiquitous, Computing
National Category
Information Systems
Identifiers
urn:nbn:se:hh:diva-1841 (URN)2082/2236 (Local ID)2082/2236 (Archive number)2082/2236 (OAI)
Note
Teknisk rapport gjord på uppdrag från projektet UbiMedia.Available from: 2008-09-03 Created: 2008-09-03 Last updated: 2018-03-23Bibliographically approved
Wecksten, M. (2008). Är du beredd? – för nu snor någon dina företagshemligheter!. Hallands Affärer (3), pp. 1
Open this publication in new window or tab >>Är du beredd? – för nu snor någon dina företagshemligheter!
2008 (Swedish)In: Hallands Affärer, no 3, p. 1-Article in journal, News item (Other (popular science, discussion, etc.)) Published
Abstract [sv]

Populärvetenskapligt brandtal om nyttan och behovet av välutbildade nätverkstekniker med perspektiv på såväl teknik som juridik.

Place, publisher, year, edition, pages
Halmstad: Hallandsposten, 2008
Keywords
nätverk, säkerhet, forensik, informationssäkerhet
National Category
Other Computer and Information Science
Identifiers
urn:nbn:se:hh:diva-1883 (URN)2082/2278 (Local ID)2082/2278 (Archive number)2082/2278 (OAI)
Available from: 2008-09-11 Created: 2008-09-11 Last updated: 2018-03-23Bibliographically approved
Kunert, K., Weckstén, M. & Jonsson, M. (2007). Algorithm for the choice of topology in reconfigurable networks with real-time support.
Open this publication in new window or tab >>Algorithm for the choice of topology in reconfigurable networks with real-time support
2007 (English)Report (Other academic)
Abstract [en]

Many future embedded systems are likely to contain System-on-Chip solutions with on-chip networks, and to achieve high aggregated throughputs in these networks, a switched topology can be used. For further performance improvements, the topology can be adapted to application demands, either when designing the chip or by run-time reconfiguration between different predefined application modes. In this report, we describe an algorithm for the choice of topology in, e.g., packet-switched on-chip networks, considering the real-time demands in terms of throughput and delay often put on such systems. To further address possible real-time demands, we include a feasibility analysis to check that the application, when mapped onto the system, will behave in line with its real-time demands. With input information about the traffic characteristics, our algorithm creates a topology and generates routing information for all logical traffic channels. In a case study, we show that our algorithm results in a topology that can outperform the use of state of the art topologies for high-performance computer architectures. Although we have targeted for reconfigurable Network-on-Chip architectures, the algorithm can also be used for other systems. Our algorithm gives the opportunity for topology choice at design stage, both for static network topologies and for reconfigurable network topologies that can be reconfigured during run-time.

Publisher
p. 22
Series
Research Report, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad University, Sweden ; IDE - 0786
Keywords
Real-time communication, NoC, network-on-chip, embedded systems
National Category
Computer Engineering
Identifiers
urn:nbn:se:hh:diva-52 (URN)
Available from: 2009-08-25 Created: 2009-08-24 Last updated: 2018-03-23Bibliographically approved
Kunert, K., Weckstén, M. & Jonsson, M. (2007). Algorithm for the choice of topology in reconfigurable on-chip networks with real-time support. In: Proceedings of the 2nd international conference on Nano-Networks. Paper presented at Nanonet07 Second International Conference on Nano-NetworksCatania, Italy, September 24 - 26, 2007 (pp. 1-7). Bryssels: ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering)
Open this publication in new window or tab >>Algorithm for the choice of topology in reconfigurable on-chip networks with real-time support
2007 (English)In: Proceedings of the 2nd international conference on Nano-Networks, Bryssels: ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering) , 2007, p. 1-7Conference paper, Published paper (Refereed)
Abstract [en]

Many future embedded systems are likely to contain System-on-Chip solutions with on-chip networks and in order to achieve high aggregated throughputs in these networks, a switched topology can be used. For further performance improvements, the topology can be adapted to application demands, either when designing the chip or by run-time reconfiguration between different predefined application modes. In this paper, we present an algorithm for the choice of topology in, e.g., on-chip networks, considering realtime demands in terms of throughput and delay often put on such systems. To further address possible real-time demands, we include a feasibility analysis to check that the application, when mapped onto the system, will behave in line with its real-time demands. With input information about traffic characteristics, our algorithm creates a topology and generates routing information for all logical traffic channels. In a case study, we show that our algorithm results in a topology that can outperform the use of state of the art topologies for high-performance computer architectures.

Place, publisher, year, edition, pages
Bryssels: ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering), 2007
Keywords
Network-on-Chip, topology design, feasibility analysis, real-time communication, reconfigurable systems
National Category
Engineering and Technology
Identifiers
urn:nbn:se:hh:diva-2225 (URN)2082/2623 (Local ID)978-963-9799-10-3 (ISBN)2082/2623 (Archive number)2082/2623 (OAI)
Conference
Nanonet07 Second International Conference on Nano-NetworksCatania, Italy, September 24 - 26, 2007
Available from: 2010-09-27 Created: 2009-01-27 Last updated: 2018-03-23Bibliographically approved
Weckstén, M., Jonsson, M. & Vasell, J. (2007). Derivation of implementation constraints – implementation simulation and treatment of multiple design choices. In: Proc. of the 9th biennial SNART Conference on Real-Time Systems (Real-Time in Sweden – RTiS’07), Västerås, Sweden, Aug. 21-22. Paper presented at 9th biennial SNART Conference on Real-Time Systems (Real-Time in Sweden – RTiS’07), Västerås, Sweden, Aug. 21-22 (pp. 21-28).
Open this publication in new window or tab >>Derivation of implementation constraints – implementation simulation and treatment of multiple design choices
2007 (English)In: Proc. of the 9th biennial SNART Conference on Real-Time Systems (Real-Time in Sweden – RTiS’07), Västerås, Sweden, Aug. 21-22, 2007, p. 21-28Conference paper, Published paper (Refereed)
Abstract [en]

The industrial use of ad hoc implementation methods for non-functional constrained tasks has resulted in unnecessary expensive projects. In some cases, ad hoc methods result in overly many iterations to be made and in some severe cases, total project breakdown. To be able to solve these problems a method has been developed to derive end-to-end non-functional constraints, such as timing requirements, to task-level constraints and to promote this information to the implementation phase of the project. For a tool, as the one described above, to be really useful it is important to be able to show that there is a potential cost reduction to be made. To be able to show that a certain implementation method costs less in work hours than to use an ad hoc implementation method, a model for implementation simulation with support for multiple implementation alternatives has been developed. The experiments show that using the budget based implementation method leads to a significant cost reduction in most cases, compared to the ad hoc method. As far as we know, no similar experiments has been done to compare implementation methods.

Keywords
Real-time
National Category
Computer Engineering
Identifiers
urn:nbn:se:hh:diva-2732 (URN)2082/3134 (Local ID)2082/3134 (Archive number)2082/3134 (OAI)
Conference
9th biennial SNART Conference on Real-Time Systems (Real-Time in Sweden – RTiS’07), Västerås, Sweden, Aug. 21-22
Available from: 2009-08-12 Created: 2009-08-12 Last updated: 2018-03-23Bibliographically approved
Weckstén, M., Jonsson, M. & Vasell, J. (2005). Derivation of implementation constraints - implementation simulation and treatment of multiple design choices. In: Proceedings: 10th IEEE International Conference on Engineering of Complex Computer Systems, ICECCS 2005, 16-20 June 2005, Shanghai, China. Paper presented at 10th IEEE International Conference on Engineering of Complex Computer Systems, ICECCS 2005, 16-20 June 2005, Shanghai, China (pp. 459-466). Los Alamitos, Calif.: IEEE Computer Society
Open this publication in new window or tab >>Derivation of implementation constraints - implementation simulation and treatment of multiple design choices
2005 (English)In: Proceedings: 10th IEEE International Conference on Engineering of Complex Computer Systems, ICECCS 2005, 16-20 June 2005, Shanghai, China, Los Alamitos, Calif.: IEEE Computer Society, 2005, p. 459-466Conference paper, Published paper (Refereed)
Abstract [en]

The industrial use of ad hoc implementation methods for non-functional constrained tasks has resulted in unnecessary expensive projects. In some cases, ad hoc methods result in overly many iterations to be made and in some severe cases, total project breakdown. To be able to solve these problems a method has been developed to derive end-to-end non-functional constraints, such as timing requirements, to task-level constraints and to promote this information to the implementation phase of the project. For a tool, as the one described above, to be really useful it is important to be able to show that there is a potential cost reduction to be made. To be able to show that a certain implementation method costs less in work hours than to use an ad hoc implementation method, a model for implementation simulation with support for multiple implementation alternatives has been developed. The experiments show that using the budget based implementation method leads to a significant cost reduction in most cases, compared to the ad hoc method. As far as we know, no similar experiments have been done to compare implementation methods.

Place, publisher, year, edition, pages
Los Alamitos, Calif.: IEEE Computer Society, 2005
Series
IEEE International Conference on Engineering Complex Computer Systems-ICECCS
Keywords
Constraint handling, Functional programming, Software cost estimation, Software management
National Category
Computer Sciences
Identifiers
urn:nbn:se:hh:diva-382 (URN)10.1109/ICECCS.2005.32 (DOI)000230787600060 ()2-s2.0-27144516382 (Scopus ID)2082/706 (Local ID)0-7695-2284-X (ISBN)2082/706 (Archive number)2082/706 (OAI)
Conference
10th IEEE International Conference on Engineering of Complex Computer Systems, ICECCS 2005, 16-20 June 2005, Shanghai, China
Note

©2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

Available from: 2007-01-11 Created: 2007-01-11 Last updated: 2018-03-23Bibliographically approved
Weckstén, M., Vassell, J. & Jonsson, M. (2004). A tool for derivation of implementation constraints: – evaluation using implementation simulation. In: RTSS 2004 WIP Proceedings, The 25th IEEE International Real-Time Systems Symposium. Paper presented at The 25th IEEE International Real-Time Systems Symposium (pp. 4). IEEE
Open this publication in new window or tab >>A tool for derivation of implementation constraints: – evaluation using implementation simulation
2004 (English)In: RTSS 2004 WIP Proceedings, The 25th IEEE International Real-Time Systems Symposium, IEEE , 2004, p. 4-Conference paper, Published paper (Refereed)
Abstract [en]

The industrial use of ad hoc implementation methods for non-functional constrained tasks has sometimes resulted in unnecessary expensive projects. In some cases, ad hoc methods result in overly many iterations to be made and in some severe cases, total project breakdown. To be able to solve these problems a new method has been developed to derive end-to-end non-functional constraints, such as performance or resource utilization requirements, to task-level constraints and to promote this information to the implementation phase of the project. For a tool to be really useful it is important to be able to show the usability and potential cost reduction. To be able to show that a certain implementation method costs less in work hours than to use an ad hoc implementation method, a model for implementation simulation has been developed. As far as we know, no similar experiments has been done to compare implementation methods.

Place, publisher, year, edition, pages
IEEE, 2004
Keywords
Real-time
National Category
Computer Engineering
Identifiers
urn:nbn:se:hh:diva-2739 (URN)2082/3141 (Local ID)2082/3141 (Archive number)2082/3141 (OAI)
Conference
The 25th IEEE International Real-Time Systems Symposium
Available from: 2009-08-12 Created: 2009-08-12 Last updated: 2018-03-23Bibliographically approved
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