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Bengtsson, Jerker
Publications (10 of 14) Show all publications
Svensson, B., Ul-Abdin, Z., Ericsson, P. M., Åhlander, A., Hoang Bengtsson, H., Bengtsson, J., . . . Nordström, T. (2014). A Running Leap for Embedded Signal Processing to Future Parallel Platforms. In: WISE'14: Proceedings of the 2014 ACM International Workshop on Long-Term Industrial Collaboration on Software Engineering. Paper presented at ASE '14 – ACM/IEEE International Conference on Automated Software Engineering, Västerås, Sweden, September 15-19, 2014 (pp. 35-42). New York, NY: Association for Computing Machinery (ACM)
Open this publication in new window or tab >>A Running Leap for Embedded Signal Processing to Future Parallel Platforms
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2014 (English)In: WISE'14: Proceedings of the 2014 ACM International Workshop on Long-Term Industrial Collaboration on Software Engineering, New York, NY: Association for Computing Machinery (ACM), 2014, p. 35-42Conference paper, Published paper (Refereed)
Abstract [en]

This paper highlights the collaboration between industry and academia in research. It describes more than two decades of intensive development and research of new hardware and software platforms to support innovative, high-performance sensor systems with extremely high demands on embedded signal processing capability. The joint research can be seen as the run before a necessary jump to a new kind of computational platform based on parallelism. The collaboration has had several phases, starting with a focus on hardware, then on efficiency, later on software development, and finally on taking the jump and understanding the expected future. In the first part of the paper, these phases and their respective challenges and results are described. Then, in the second part, we reflect upon the motivation for collaboration between company and university, the roles of the partners, the experiences gained and the long-term effects on both sides. Copyright © 2014 ACM.

Place, publisher, year, edition, pages
New York, NY: Association for Computing Machinery (ACM), 2014
Keywords
Industry-academia collaboration, Embedded signal processing, Parallel computing platforms, Software development
National Category
Software Engineering
Identifiers
urn:nbn:se:hh:diva-27296 (URN)10.1145/2647648.2647653 (DOI)2-s2.0-84908651240 (Scopus ID)978-1-4503-3045-9 (ISBN)
Conference
ASE '14 – ACM/IEEE International Conference on Automated Software Engineering, Västerås, Sweden, September 15-19, 2014
Funder
VINNOVAKnowledge FoundationSwedish Foundation for Strategic Research
Available from: 2014-12-16 Created: 2014-12-16 Last updated: 2018-03-22Bibliographically approved
Bengtsson, J. & Hoang Bengtsson, H. (2010). Dynamic Real-time DSP on Manycores. Paper presented at THIRD SWEDISH WORKSHOP ON MULTI-CORE COMPUTING - MCC'10, 18-19 November, 2010, Chalmers Conference Center, Scania Conference Room, Göteborg, Sweden. Gothenburg
Open this publication in new window or tab >>Dynamic Real-time DSP on Manycores
2010 (English)Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
Gothenburg: , 2010
National Category
Engineering and Technology
Identifiers
urn:nbn:se:hh:diva-14625 (URN)
Conference
THIRD SWEDISH WORKSHOP ON MULTI-CORE COMPUTING - MCC'10, 18-19 November, 2010, Chalmers Conference Center, Scania Conference Room, Göteborg, Sweden
Available from: 2011-03-23 Created: 2011-03-23 Last updated: 2018-03-23Bibliographically approved
Bengtsson, J. (2010). Intermediate representations for simulation and implementation (1ed.). In: S.S Bhattacharyya, E.F. Deprettere, R. Leupers and J. Takala (Ed.), Handbook of Signal processing systems (pp. 739-767). New York: Springer-Verlag New York
Open this publication in new window or tab >>Intermediate representations for simulation and implementation
2010 (English)In: Handbook of Signal processing systems / [ed] S.S Bhattacharyya, E.F. Deprettere, R. Leupers and J. Takala, New York: Springer-Verlag New York, 2010, 1, p. 739-767Chapter in book (Other academic)
Place, publisher, year, edition, pages
New York: Springer-Verlag New York, 2010 Edition: 1
Keywords
DSP systems, DSP platforms, Simulation, Implementation
National Category
Computer Engineering
Identifiers
urn:nbn:se:hh:diva-5986 (URN)10.1007/978-1-4419-6345-1 (DOI)978-1-4419-6344-4 (ISBN)978-1-4419-6345-1 (ISBN)
Available from: 2010-09-23 Created: 2010-09-23 Last updated: 2018-03-23Bibliographically approved
Bengtsson, J. & Svensson, B. (2009). Manycore performance analysis using timed configuration graphs. In: Michael Joseph Schulte and Walid Najjar (Ed.), International Symposium on Systems, Architectures, Modeling, and Simulation, 2009. SAMOS '09. Paper presented at 2009 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2009, Samos, 20 - 23 July, 2009 (pp. 108-117). Piscataway, N.J.: IEEE Press
Open this publication in new window or tab >>Manycore performance analysis using timed configuration graphs
2009 (English)In: International Symposium on Systems, Architectures, Modeling, and Simulation, 2009. SAMOS '09 / [ed] Michael Joseph Schulte and Walid Najjar, Piscataway, N.J.: IEEE Press, 2009, p. 108-117Conference paper, Published paper (Refereed)
Abstract [en]

The programming complexity of increasingly parallel processors calls for new tools to assist programmers in utilising the parallel hardware resources. In this paper we present a set of models that we have developed to form part of a tool which is intended for iteratively tuning the mapping of dataflow graphs onto manycores. One of the models is used for capturing the essentials of manycores that are identified as suitable for signal processing and which we use as target architectures. Another model is the intermediate representation in the form of a timed configuration graph, describing the mapping of a dataflow graph onto a machine model. Moreover, this IR can be used for performance evaluation using abstract interpretation. We demonstrate how the models can be configured and applied in order to map applications on the Raw processor. Furthermore, we report promising results on the accuracy of performance predictions produced by our tool. It is also demonstrated that the tool can be used to rank different mappings with respect to optimisation on throughput and end-to-end latency.

Place, publisher, year, edition, pages
Piscataway, N.J.: IEEE Press, 2009
Keywords
graphs, microcomputers, parallel architectures, parallel programming, program compilers, software performance evaluation, task analysis
National Category
Computer Engineering
Identifiers
urn:nbn:se:hh:diva-5987 (URN)10.1109/ICSAMOS.2009.5289221 (DOI)000276377000014 ()2-s2.0-71949094275 (Scopus ID)978-1-4244-4502-8 (ISBN)
Conference
2009 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2009, Samos, 20 - 23 July, 2009
Note

©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

Available from: 2010-09-23 Created: 2010-09-23 Last updated: 2018-03-23Bibliographically approved
Bengtsson, J. (2009). Models and Methods for Development of DSP Applications on Manycore Processors. (Doctoral dissertation). Göteborg: Chalmers University of Technology
Open this publication in new window or tab >>Models and Methods for Development of DSP Applications on Manycore Processors
2009 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Advanced digital signal processing systems require specialized high-performance embedded computer architectures. The term high-performance translates to large amounts of data and computations per time unit. The term embedded further implies requirements on physical size and power efficiency. Thus the requirements are of both functional and non-functional nature. This thesis addresses the development of high-performance digital signal processing systems relying on manycore technology. We propose building two-level hierarchical computer architectures for this domain of applications. Further, we outline a tool flow based on methods and analysis techniques for automated, multi-objective mapping of such applications on distributed memory manycore processors. In particular, the focus is put on how to provide a means for tunable strategies for mapping of task graphs on array structured distributed memory manycores, with respect to given application constraints. We argue for code mapping strategies based on predicted execution performance, which can be used in an auto-tuning feedback loop or to guide manual tuning directed by the programmer. Automated parallelization, optimisation and mapping to a manycore processor benefits from the use of a concurrent programming model as the starting point. Such a model allows the programmer to express different types and granularities of parallelism as well as computation characteristics of importance in the addressed class of applications. The programming model should also abstract away machine dependent hardware details. The analytical study of WCDMA baseband processing in radio base stations, presented in this thesis, suggests dataflow models as a good match to the characteristics of the application and as execution model abstracting computations on a manycore. Construction of portable tools further requires a manycore machine model and an intermediate representation. The models are needed in order to decouple algorithms, used to transform and map application software, from hardware. We propose a manycore machine model that captures common hardware resources, as well as resource dependent performance metrics for parallel computation and communication. Further, we have developed a multifunctional intermediate representation, which can be used as source for code generation and for dynamic execution analysis. Finally, we demonstrate how we can dynamically analyse execution using abstract interpretation on the intermediate representation. It is shown that the performance predictions can be used to accurately rank different mappings by best throughput or shortest end-to-end computation latency.

Place, publisher, year, edition, pages
Göteborg: Chalmers University of Technology, 2009. p. 173
Series
Doktorsavhandlingar vid Chalmers tekniska högskola. Ny serie, ISSN 0346-718X ; 2969
Keywords
parallel processing, manycore processors, high-performance digital signal processing, dataflow, concurrent models of computation, parallel code mapping, parallel machine model, dynamic performance analysis
National Category
Computer Engineering
Identifiers
urn:nbn:se:hh:diva-14706 (URN)978-91-7385-288-3 (ISBN)
Public defence
2009-06-10, Wigforssalen, house Visionen, Halmstad University, Kristian IV:s väg 3, Halmstad, 13:15 (English)
Opponent
Supervisors
Available from: 2011-04-20 Created: 2011-04-04 Last updated: 2018-03-23Bibliographically approved
Bengtsson, J. & Svensson, B. (2008). A domain-specic approach for software development on manycore platforms. Paper presented at First Swedish Workshop on Multi-Core Computing MCC-08 November 27-28, 2008 Ronneby, Sweden. New York: ACM Press
Open this publication in new window or tab >>A domain-specic approach for software development on manycore platforms
2008 (English)Conference paper, Published paper (Refereed)
Abstract [en]

The programming complexity of increasingly parallel processors calls for new tools that assist programmers in utilising the parallel hardware resources. In this paper we present a set of models that we have developed as part of a tool for mapping dataflow graphs onto manycores. One of the models captures the essentials of manycores identified as suitable for signal processing, and which we use as tar- get for our algorithms. As an intermediate representation we introduce timed configuration graphs, which describe the mapping of a model of an application onto a machine model. Moreover, we show how a timed configuration graph by very simple means can be evaluated using an abstract interpretation to obtain performance feedback. This infor- mation can be used by our tool and by the programmer in order to discover improved mappings.

Place, publisher, year, edition, pages
New York: ACM Press, 2008
Series
ACM SIGARCH Computer Architecture News, ISSN 0163-5964 ; Vol. 36 Issue 5
National Category
Computer Engineering
Identifiers
urn:nbn:se:hh:diva-5989 (URN)10.1145/1556444.1556446 (DOI)
Conference
First Swedish Workshop on Multi-Core Computing MCC-08 November 27-28, 2008 Ronneby, Sweden
Available from: 2010-09-23 Created: 2010-09-23 Last updated: 2018-03-23Bibliographically approved
Bengtsson, J. & Svensson, B. (2008). A Domain-specific Approach for Software Development on Manycore Platforms. Paper presented at Association for Computing Machinery Special Interest Group on Computer Architecture. SIGARCH Computer Architecture News, 36(5), 2-10
Open this publication in new window or tab >>A Domain-specific Approach for Software Development on Manycore Platforms
2008 (English)In: SIGARCH Computer Architecture News, ISSN 0163-5964, E-ISSN 1943-5851, Vol. 36, no 5, p. 2-10Article in journal (Refereed) Published
Abstract [en]

The programming complexity of increasingly parallel processors calls for new tools that assist programmers in utilising the parallel hardware resources. In this paper we present a set of models that we have developed as part of a tool for mapping dataflow graphs onto manycores. One of the models captures the essentials of manycores identified as suitable for signal processing, and which we use as target for our algorithms. As an intermediate representation we introduce timed configuration graphs, which describe the mapping of a model of an application onto a machine model. Moreover, we show how a timed configuration graph by very simple means can be evaluated using an abstract interpretation to obtain performance feedback. This information can be used by our tool and by the programmer in order to discover improved mappings.

Place, publisher, year, edition, pages
New York: ACM Press, 2008
Keywords
Programming, Manycores
National Category
Computer Engineering
Identifiers
urn:nbn:se:hh:diva-5990 (URN)10.1145/1556444.1556446 (DOI)
Conference
Association for Computing Machinery Special Interest Group on Computer Architecture
Available from: 2010-09-23 Created: 2010-09-23 Last updated: 2018-03-23Bibliographically approved
Bengtsson, J. & Svensson, B. (2008). Methodologies and tools for development of signal processing software on multicore platforms. In: 2008 proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture: MICRO-41, November 8-12, 2008, Lake Como, Italy. Paper presented at Workshop on Streaming Systems in conjunction with the 41st Annual IEEE/ACM International Symposium on Michroarchitecture (MICRO), Lake Como, Italy, November 08 - 12, 2008 (pp. 2). Piscataway, N.J.: IEEE Computer Society
Open this publication in new window or tab >>Methodologies and tools for development of signal processing software on multicore platforms
2008 (English)In: 2008 proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture: MICRO-41, November 8-12, 2008, Lake Como, Italy, Piscataway, N.J.: IEEE Computer Society, 2008, p. 2-Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
Piscataway, N.J.: IEEE Computer Society, 2008
National Category
Computer Engineering
Identifiers
urn:nbn:se:hh:diva-14697 (URN)978-1-4244-2836-6 (ISBN)
Conference
Workshop on Streaming Systems in conjunction with the 41st Annual IEEE/ACM International Symposium on Michroarchitecture (MICRO), Lake Como, Italy, November 08 - 12, 2008
Available from: 2011-09-06 Created: 2011-04-02 Last updated: 2018-03-23Bibliographically approved
Hoang, H. & Bengtsson, J. (2008). On supporting real-time communication over the IEEE 802.15.4 protocol. In: Proceedings of the international conference on wireless information networks and systems (WinSys 2008). Paper presented at International Conference on Wireless Information Networks and Systems, Oporto, Portugal, jul 26-29, 2008 (pp. 82-87). Setubal: INSTICC Press
Open this publication in new window or tab >>On supporting real-time communication over the IEEE 802.15.4 protocol
2008 (English)In: Proceedings of the international conference on wireless information networks and systems (WinSys 2008), Setubal: INSTICC Press, 2008, p. 82-87Conference paper, Published paper (Refereed)
Abstract [en]

IEEE 802.15.4 is a new enabling technology for low data rate wireless personal networks. This standard was not specifically designed for wireless sensor networks, but it has shown to be a good match with necessary requirements on low data rate, low power consumption and low cost. Unlike the former 802.11 standard, the MAC protocol specified in IEEE 802.15.4 can operate in two different modes: beacon-enabled mode or non-beacon enable mode. In beacon-enabled mode, nodes can exclusively allocate a number of guaranteed time slots, similar to a resource reservation scheme. Hence, the IEEE 802.15.4 MAC protocol have sufficient capabilities for supporting real-time communication. This paper presents the key features of IEEE 802.15.4 which makes it an attractive standard to use for real-time wireless sensor networks. Two real-time protocols extending the IEEE 802.15.4 standard are reviewed. The purpose of this paper is to present the state of the art on real-time support over IEEE 802.15.4 for wireless sensor networks and to discuss the possibilities on improvements on both the standard and the real-time protocols extending the standard.

Place, publisher, year, edition, pages
Setubal: INSTICC Press, 2008
Keywords
QoS, Real-time communication, Wireless network
National Category
Telecommunications
Identifiers
urn:nbn:se:hh:diva-2704 (URN)000258910000016 ()2-s2.0-58049148144 (Scopus ID)2082/3106 (Local ID)978-989-8111-62-3 (ISBN)2082/3106 (Archive number)2082/3106 (OAI)
Conference
International Conference on Wireless Information Networks and Systems, Oporto, Portugal, jul 26-29, 2008
Available from: 2009-07-06 Created: 2009-07-06 Last updated: 2018-03-23Bibliographically approved
Bengtsson, J., Gaspes, V. & Svensson, B. (2007). Machine Assisted Code Generation for Manycore Processors. In: Proceedings of the 9th biennial SNART Conference on Real-Time Systems (Real-Time in Sweden - RTiS'07). Paper presented at 9th biennial SNART Conference on Real-Time Systems (Real-Time in Sweden - RTiS'07) August 21-22, Västerås, Sweden (pp. 9).
Open this publication in new window or tab >>Machine Assisted Code Generation for Manycore Processors
2007 (English)In: Proceedings of the 9th biennial SNART Conference on Real-Time Systems (Real-Time in Sweden - RTiS'07), 2007, p. 9-Conference paper, Published paper (Refereed)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:hh:diva-2716 (URN)2082/3118 (Local ID)2082/3118 (Archive number)2082/3118 (OAI)
Conference
9th biennial SNART Conference on Real-Time Systems (Real-Time in Sweden - RTiS'07) August 21-22, Västerås, Sweden
Available from: 2009-07-06 Created: 2009-07-06 Last updated: 2018-03-23Bibliographically approved

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