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Åhlander, Anders
Publications (10 of 15) Show all publications
Svensson, B., Ul-Abdin, Z., Ericsson, P. M., Åhlander, A., Hoang Bengtsson, H., Bengtsson, J., . . . Nordström, T. (2014). A Running Leap for Embedded Signal Processing to Future Parallel Platforms. In: WISE'14: Proceedings of the 2014 ACM International Workshop on Long-Term Industrial Collaboration on Software Engineering. Paper presented at ASE '14 – ACM/IEEE International Conference on Automated Software Engineering, Västerås, Sweden, September 15-19, 2014 (pp. 35-42). New York, NY: Association for Computing Machinery (ACM)
Open this publication in new window or tab >>A Running Leap for Embedded Signal Processing to Future Parallel Platforms
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2014 (English)In: WISE'14: Proceedings of the 2014 ACM International Workshop on Long-Term Industrial Collaboration on Software Engineering, New York, NY: Association for Computing Machinery (ACM), 2014, p. 35-42Conference paper, Published paper (Refereed)
Abstract [en]

This paper highlights the collaboration between industry and academia in research. It describes more than two decades of intensive development and research of new hardware and software platforms to support innovative, high-performance sensor systems with extremely high demands on embedded signal processing capability. The joint research can be seen as the run before a necessary jump to a new kind of computational platform based on parallelism. The collaboration has had several phases, starting with a focus on hardware, then on efficiency, later on software development, and finally on taking the jump and understanding the expected future. In the first part of the paper, these phases and their respective challenges and results are described. Then, in the second part, we reflect upon the motivation for collaboration between company and university, the roles of the partners, the experiences gained and the long-term effects on both sides. Copyright © 2014 ACM.

Place, publisher, year, edition, pages
New York, NY: Association for Computing Machinery (ACM), 2014
Keywords
Industry-academia collaboration, Embedded signal processing, Parallel computing platforms, Software development
National Category
Software Engineering
Identifiers
urn:nbn:se:hh:diva-27296 (URN)10.1145/2647648.2647653 (DOI)2-s2.0-84908651240 (Scopus ID)978-1-4503-3045-9 (ISBN)
Conference
ASE '14 – ACM/IEEE International Conference on Automated Software Engineering, Västerås, Sweden, September 15-19, 2014
Funder
VINNOVAKnowledge FoundationSwedish Foundation for Strategic Research
Available from: 2014-12-16 Created: 2014-12-16 Last updated: 2018-03-22Bibliographically approved
Ul-Abdin, Z., Åhlander, A. & Svensson, B. (2013). Energy-Efficient Synthetic-Aperture Radar Processing on a Manycore Architecture. In: Randall Bilof (Ed.), Proceedings: International Conference on Parallel Processing : The 42nd Annual Conference : ICPP 2013 : 1-4 October 2013 : Lyon, France. Paper presented at 2013 International Conference on Parallel Processing (ICPP-2013), The 42nd Annual Conference, October 1-4, 2013, École Normale Supérieure de Lyon, Lyon, France (pp. 330-338). Piscataway, NJ: IEEE conference proceedings, Article ID 6687366.
Open this publication in new window or tab >>Energy-Efficient Synthetic-Aperture Radar Processing on a Manycore Architecture
2013 (English)In: Proceedings: International Conference on Parallel Processing : The 42nd Annual Conference : ICPP 2013 : 1-4 October 2013 : Lyon, France / [ed] Randall Bilof, Piscataway, NJ: IEEE conference proceedings, 2013, p. 330-338, article id 6687366Conference paper, Published paper (Refereed)
Abstract [en]

The next generation radar systems have high performance demands on the signal processing chain. Examples include the advanced image creating sensor systems in which complex calculations are to be performed on huge sets of data in realtime. Manycore architectures are gaining attention as a means to overcome the computational requirements of the complex radar signal processing by exploiting massive parallelism inherent in the algorithms in an energy efficient manner.

In this paper, we evaluate a manycore architecture, namely a 16-core Epiphany processor, by implementing two significantly large case studies, viz. an autofocus criterion calculation and the fast factorized back-projection algorithm, both key componentsin modern synthetic aperture radar systems. The implementation results from the two case studies are compared on the basis of achieved performance and programmability. One of the Epiphany implementations demonstrates the usefulness of the architecture for the streaming based algorithm (the autofocus criterion calculation) by achieving a speedup of 8.9x over a sequential implementation on a state-of-the-art general-purpose processor of a later silicon technology generation and operating at a 2.7x higher clock speed. On the other case study, a highly memory-intensive algorithm (fast factorized backprojection), the Epiphany architecture shows a speedup of 4.25x. For embedded signal processing, low power dissipation is equally important as computational performance. In our case studies, the Epiphany implementations of the two algorithms are, respectively, 78x and 38x more energy efficient. © 2013 IEEE

Place, publisher, year, edition, pages
Piscataway, NJ: IEEE conference proceedings, 2013
Series
International Conference on Parallel Processing. Proceedings, ISSN 0190-3918
Keywords
Manycore architecture, Parallel programming, Radar signal processing
National Category
Embedded Systems
Identifiers
urn:nbn:se:hh:diva-23888 (URN)10.1109/ICPP.2013.42 (DOI)000330046000033 ()2-s2.0-84893267719 (Scopus ID)978-0-7695-5117-3 (ISBN)978-1-4799-1448-7 (ISBN)
Conference
2013 International Conference on Parallel Processing (ICPP-2013), The 42nd Annual Conference, October 1-4, 2013, École Normale Supérieure de Lyon, Lyon, France
Available from: 2013-10-30 Created: 2013-10-30 Last updated: 2018-03-22Bibliographically approved
Ul-Abdin, Z., Åhlander, A. & Svensson, B. (2013). Real-time Radar Signal Processing on Massively Parallel Processor Arrays. In: Michael B. Matthews (Ed.), Conference Record of The Forty-Seventh Asilomar Conference on Signals, Systems & Computers: November 3–6, 2013 Pacific Grove, California. Paper presented at 47th IEEE Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, November 3–6, 2013 (pp. 1810-1814). Piscataway, NJ: IEEE Signal Processing Society
Open this publication in new window or tab >>Real-time Radar Signal Processing on Massively Parallel Processor Arrays
2013 (English)In: Conference Record of The Forty-Seventh Asilomar Conference on Signals, Systems & Computers: November 3–6, 2013 Pacific Grove, California / [ed] Michael B. Matthews, Piscataway, NJ: IEEE Signal Processing Society, 2013, p. 1810-1814Conference paper, Published paper (Refereed)
Abstract [en]

The next generation radar systems have high performance demands on the signal processing chain. Among these are advanced image creating sensor systems in which complex calculations are to be performed on huge sets of data in realtime. Massively Parallel Processor Arrays (MPPAs) are gaining attention to cope with the computational requirements of complex radar signal processing by exploiting the massive parallelism inherent in the algorithms in an energy efficient manner.

In this paper, we evaluate two such massively parallel architectures, namely, Ambric and Epiphany, by implementing a significantly large case study of autofocus criterion calculation, which is a key component in future synthetic aperture radar systems. The implementation results from the two case studies are compared on the basis of achieved performance, energy efficiency, and programmability. ©2013 IEEE.

Place, publisher, year, edition, pages
Piscataway, NJ: IEEE Signal Processing Society, 2013
National Category
Embedded Systems
Identifiers
urn:nbn:se:hh:diva-24017 (URN)10.1109/ACSSC.2013.6810614 (DOI)978-1-4799-2390-8 (ISBN)978-1-4799-2388-5 (ISBN)
Conference
47th IEEE Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, November 3–6, 2013
Projects
JUMP (JUmp to Manycore Platforms)
Funder
Knowledge Foundation
Note

The authors would like to thank Nethra Imaging Inc. and Adapteva Inc. for giving access to their software development suite and hardware board. This research is done in the JUMP (JUmp to Manycore Platforms) project within the CERES research program supported by the Knowledge Foundation in cooperation with Saab AB.

Available from: 2013-11-27 Created: 2013-11-27 Last updated: 2018-03-22Bibliographically approved
Zain-ul-Abdin, ., Åhlander, A. & Svensson, B. (2011). Programming Real-time Autofocus on a Massively Parallel Reconfigurable Architecture using Occam-pi. In: Proceedings of the 19th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM'2011). Paper presented at IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM'2011), Campus Univ Utah, Salt Lake City, UT, MAY 01-03, 2011 (pp. 194-201). Los Alamitos, Calif.: IEEE Computer Society
Open this publication in new window or tab >>Programming Real-time Autofocus on a Massively Parallel Reconfigurable Architecture using Occam-pi
2011 (English)In: Proceedings of the 19th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM'2011), Los Alamitos, Calif.: IEEE Computer Society, 2011, p. 194-201Conference paper, Published paper (Refereed)
Abstract [en]

Recently we proposed occam-pi as a high-level language for programming massively parallel reconfigurable architectures. The design of occam-pi incorporates ideas from CSP and pi-calculus to facilitate expressing parallelism and reconfigurability. The feasability of this approach was illustratedby building three occam-pi implementations of DCT executing on an Ambric. However, because DCT is a simple and well studied algorithm it remained uncertain whether occam-pi would also be effective for programming novel, more complex algorithms.

In this paper, we demonstrate the applicability of occam-pi for expressing various degrees of parallelism by implementinga significantly large case-study of focus criterion calculation inan autofocus algorithm on the Ambric architecture. Autofocus is a key component of synthetic aperture radar systems. Two implementations of focus criterion calculation were developedand evaluated on the basis of performance. The comparison of the performance results with a single threaded software implementation of the same algorithm show that the throughput of the two implementations are 11x and 23x higher than the sequential implementation despite a much lower (9x) clock frequency. The two designs are, respectively, 29x and 40x moreenergy efficient.

Place, publisher, year, edition, pages
Los Alamitos, Calif.: IEEE Computer Society, 2011
Series
Annual IEEE Symposium on Field-Programmable Custom Computing Machines
National Category
Computer Engineering
Identifiers
urn:nbn:se:hh:diva-14616 (URN)10.1109/FCCM.2011.20 (DOI)000298664800034 ()2-s2.0-79958730167 (Scopus ID)978-1-61284-277-6 (ISBN)978-0-7695-4301-7 (ISBN)
Conference
IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM'2011), Campus Univ Utah, Salt Lake City, UT, MAY 01-03, 2011
Projects
SMECY
Funder
EU, FP7, Seventh Framework Programme, 100230
Note

©2011 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

Available from: 2011-03-22 Created: 2011-03-22 Last updated: 2018-03-23Bibliographically approved
Åhlander, A., Hellsten, H., Lind, K., Lindgren, J. & Svensson, B. (2007). Architectural challenges in memory-intensive, real-time image forming. In: Li Jiandong (Ed.), International Conference on Parallel Processing, 2007. ICPP 2007 (pp. 35-45). IEEE Press
Open this publication in new window or tab >>Architectural challenges in memory-intensive, real-time image forming
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2007 (English)In: International Conference on Parallel Processing, 2007. ICPP 2007 / [ed] Li Jiandong, IEEE Press, 2007, p. 35-45Conference paper, Published paper (Refereed)
Abstract [en]

The real-time image forming in future, high-end synthetic aperture radar systems is an example of an application that puts new demands on computer architectures. The initial question is whether it is at all possible to meet the demands with state-of-the-art technology or foreseeable new technology. It is therefore crucial to understand the computational flow, with its associated memory, bandwidth and processing demands. In this paper we analyse the application in order to, primarily, understand the algorithms and identify the challenges they present on a basic architectural level. The processing in the radar system is characterized by working on huge data sets, having complex memory access patterns, and doing real-time compensations for flight path errors. We propose algorithm solutions and execution schemes in interplay with a two-level (coarse-grain/fine-grain) system parallelization approach, and we provide approximate models on which the demands are quantified. In particular, we consider the choice of method for the performance-intensive data interpolations. This choice presents a trade-off problem between computational performance and size of working memory. The results of this "upstream" study will serve as a basis for further, more detailed architecture studies.

Place, publisher, year, edition, pages
IEEE Press, 2007
Series
International Conference on Parallel Processing, ISSN 0190-3918 ; 2007
Keywords
Real-Time Image Forming
National Category
Engineering and Technology
Identifiers
urn:nbn:se:hh:diva-1960 (URN)10.1109/ICPP.2007.18 (DOI)000267695300035 ()2-s2.0-47249137450 (Scopus ID)2082/2355 (Local ID)978-0-7695-2933-2 (ISBN)2082/2355 (Archive number)2082/2355 (OAI)
Note

©2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

Available from: 2008-09-26 Created: 2008-09-26 Last updated: 2018-03-23Bibliographically approved
Åhlander, A. (2007). Efficient parallell architectures for future radar signal processing. (Doctoral dissertation). Göteborg: Chalmers university of technology
Open this publication in new window or tab >>Efficient parallell architectures for future radar signal processing
2007 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The processing demands on future embedded radar signal processors may stretch to several trillions of floating-point operations per second (TFLOPS). This is an increase of two to three orders of magnitude realtive to the requirements of today. Still, the tight size and power constraints are unchanged. To meet this, new, highly parallel computer systems are needed. The systems should efficiently deliver very high performance as well as being general enough. Another challenge for future signal processors is the requirement for having huge working memories that are accessed in complicated patterns.

This thesis analyses the challenges of two classes of radar signal processing applications, namely Space-Time Adaptive Processing (STAP), which represents performance-intensive applications, and Synthetic Aperture Radar (SAR) processing, which represents memory-intensive applications. In addition to the actual performance and memory aspects of the applications, the desire for low-effort application development and maintenance is taken into consideration.

A multiple SIMD architecture is proposed for the STAP calculations. This architecture gives a combination of the high computational density in the SIMD processing modules with the overall flexibility provided on the system level. An embedded signal processing system based on the architecture is shown to be capable of TFLOPS class performance using standard CMOS VLSI technology available in the year 2001. The system is, for the given application domain, considered to have the same generality as commercial off-the-shelf (COTS) hardware, but has several years of time lead over COTS with regard to the computational performance.

The studied SAR processing is characterized by operating on huge data sets and having varying, non-linear data access paths. For this, algorithm solutions and execution schemes in inerplay with a system parallelization approach are proposed. It is shown that it is possible to obtain efficient memory accesses, despite the omplicated memory access patterns. It is also shown that the computational burden from complex interpolation kernels can be reduced through extensive calculation reuse.

Efficient engineering of complex applications in this context is discussed. The use of semi-transparent, platform-based development is demonstrated for STAP and SAR, and advocated for obtaining high engineering defficiency and long system sustainability, as well as high performance efficiency.

The overall conclusion drawn from this work is that a solid knowledge of the application domain and its future requirements, in combination with an understanding of its interaction with computational architectures, potentially enables several years of lead time in the realization of new, advanced signal prodcessing products. The important requirements on programmability and sustainability must also be taken into account in order to achieve a viable signal processing solution.

Place, publisher, year, edition, pages
Göteborg: Chalmers university of technology, 2007. p. 170
Keywords
Computer architecture, radar signal processing, space-time adaptive processing, synthetic aperture radar, parallel processing, engineering efficiency
National Category
Computer Sciences
Identifiers
urn:nbn:se:hh:diva-1985 (URN)2082/2380 (Local ID)978-91-7291-934-1 (ISBN)2082/2380 (Archive number)2082/2380 (OAI)
Public defence
2007-05-29, Wigforssalen, Högskolan i Halmstad, Halmstad, 10:15 (English)
Opponent
Note

Doktorsavhandlingar vid Chalmers tekniska högskola. Ny serie, 2615, Technical report. D, 30,

Available from: 2008-09-29 Created: 2008-09-29 Last updated: 2018-03-23Bibliographically approved
Johnsson, D., Åhlander, A. & Svensson, B. (2005). Analyzing the Advantages of Run-Time Reconfiguration in Radar Signal Processing. In: S. Q. Zheng (Ed.), Proceedings of the 17th IASTED International Conference on Parallel and Distributed Computing and Systems. Paper presented at 17th IASTED International Conference on Parallel and Distributed Computing Systems, PDCS 2005, November 14-16, 2005, Phoenix, AZ, USA (pp. 701-706). Anaheim: ACTA Press
Open this publication in new window or tab >>Analyzing the Advantages of Run-Time Reconfiguration in Radar Signal Processing
2005 (English)In: Proceedings of the 17th IASTED International Conference on Parallel and Distributed Computing and Systems / [ed] S. Q. Zheng, Anaheim: ACTA Press, 2005, p. 701-706Conference paper, Published paper (Refereed)
Abstract [en]

Configurable architectures have emerged as one of the most powerful programmable signal processing platforms commercially available, obtaining their performance through the use of spatial parallelism. By changing the functionality of these devices during run-time, flexible mapping of signal processing applications can be made. The run-time flexibility puts requirements on the reconfiguration time that depend both on the application and on the mapping strategy. In this paper we analyze one such application, Space Time Adaptive Processing for radar signal processing, and show three different mappings and their requirements. The allowed time for run-time reconfiguration in these three cases varies from 1 ms down to 1 µs. Each has its own advantages, such as data reuse and optimization of computational kernels. Architectures with reconfiguration times in the order of 10 µs provide the flexibility needed for mapping the example in an efficient way, allowing for on-chip data reuse between the different processing stages.

Place, publisher, year, edition, pages
Anaheim: ACTA Press, 2005
Keywords
Reconfigurable architecture, Radar signal processing, Configuration time
National Category
Engineering and Technology
Identifiers
urn:nbn:se:hh:diva-413 (URN)2082/751 (Local ID)0-88986-525-6 (ISBN)9780889865259 (ISBN)2082/751 (Archive number)2082/751 (OAI)
Conference
17th IASTED International Conference on Parallel and Distributed Computing Systems, PDCS 2005, November 14-16, 2005, Phoenix, AZ, USA
Available from: 2007-01-23 Created: 2007-01-23 Last updated: 2018-03-23Bibliographically approved
Åhlander, A., Åström, A., Svensson, B. & Taveniku, M. (2005). Meeting Engineer Efficiency Requirements in Highly Parallel Signal Processing by Using Platforms. In: S. Q. Zheng (Ed.), Proceedings of the 17th IASTED International Conference on Parallel and Distributed Computing and Systems: November 14-16, 2005, Phoenix, AZ, USA. Paper presented at International Conference on Parallel and Distributed Computing Systems, PDCS 2005, November 14-16, 2005, Phoenix, AZ, USA (pp. 693-700). Anaheim: ACTA Press
Open this publication in new window or tab >>Meeting Engineer Efficiency Requirements in Highly Parallel Signal Processing by Using Platforms
2005 (English)In: Proceedings of the 17th IASTED International Conference on Parallel and Distributed Computing and Systems: November 14-16, 2005, Phoenix, AZ, USA / [ed] S. Q. Zheng, Anaheim: ACTA Press, 2005, p. 693-700Conference paper, Published paper (Other (popular science, discussion, etc.))
Abstract [en]

One of the driving forces behind the development of new, highly parallel architectures is the need for embedded high-performance computing. The development of advanced applications on such architectures is, however, potentially connected to high costs. Cost-effective devel opment requires tools and processes that provide engineer efficiency, in this case tools and processes that help the developer master the application complexity. Related to engineer efficiency are the important concepts of system sustainability and flexibility. To address these issues, a platform approach can be taken. The platform should offer an understandable and stable development model, and at the same time give the possibility to take advantage of the rapid technology development, including the use of new parallel architectures. Thus it must support multiple hard ware targets, and the development model should decouple application development from mapping aspects. Two radar signal processing examples, one compute-intensive STAP and one data-intensive SAR, are used to illustrate the need. The GEPARD platform is presented as an example of our approach, and we argue that the described platform is a good fit for advanced signal processing development, facilitating the desired engineer efficiency, sustainability, and flexibility.

Place, publisher, year, edition, pages
Anaheim: ACTA Press, 2005
Series
Parallel and distributed computing and systems, ISSN 1027-2658
Keywords
High performance applications, Parallel and distributed architectures, Tools for application development, Abstract platforms, Radar signal processing
National Category
Engineering and Technology
Identifiers
urn:nbn:se:hh:diva-411 (URN)2082/735 (Local ID)0-88986-525-6 (ISBN)9780889865259 (ISBN)2082/735 (Archive number)2082/735 (OAI)
Conference
International Conference on Parallel and Distributed Computing Systems, PDCS 2005, November 14-16, 2005, Phoenix, AZ, USA
Available from: 2007-01-18 Created: 2007-01-18 Last updated: 2018-03-23Bibliographically approved
Bergenhem, C., Jonsson, M., Gördén, B. & Åhlander, A. (2002). Heterogeneous real-time services in high-performance system area networks - application demands and case study definitions. Halmstad: School of Information Science, Computer and Electrical Engineering (IDE), Halmstad University
Open this publication in new window or tab >>Heterogeneous real-time services in high-performance system area networks - application demands and case study definitions
2002 (English)Report (Other academic)
Abstract [en]

To be able to verify the feasibility of high-performance networks, it is essential to evaluate them according to specific application requirements. At the same time, specifications of quite general, or understandable, application requirements are needed for the ability to make repeated analyses on different networks. Especially, heterogeneous real-time requirements must be defined to be able to analyze networks to be used in future applications. In this report, we introduce two application fields where system area networks (SANs) supporting heterogeneous real-time services are highly desirable if not required: radar signal processing and large IP routers. For each application field, a case study with heterogeneous real-time communication requirements is defined. No case studies are presented in this report. Instead, they are defined for later evaluations to determine how suitable networks are for applications with heterogeneous real-time communication requirements.

Place, publisher, year, edition, pages
Halmstad: School of Information Science, Computer and Electrical Engineering (IDE), Halmstad University, 2002. p. 10
Series
Technical Report ; IDE - 0254
Keywords
Embedded systems, interconnection networks
National Category
Computer Engineering
Identifiers
urn:nbn:se:hh:diva-51 (URN)
Available from: 2009-08-25 Created: 2009-08-24 Last updated: 2018-03-23Bibliographically approved
Forsberg, H., Svensson, B., Åhlander, A. & Jonsson, M. (2001). Radar signal processing using pipelined optical hypercube interconnects. In: Proceedings of the 15th International Parallel and Distributed Processing Symposium: IPDPS 2001 : abstracts and CD-ROM. Paper presented at 15th International Parallel and Distributed Processing Symposium, IPDPS 2001, San Francisco, United States, 23-27 April, 2001 (pp. 2043-2052). Los Alamitos, California: IEEE Computer Society Press, Article ID 925201.
Open this publication in new window or tab >>Radar signal processing using pipelined optical hypercube interconnects
2001 (English)In: Proceedings of the 15th International Parallel and Distributed Processing Symposium: IPDPS 2001 : abstracts and CD-ROM, Los Alamitos, California: IEEE Computer Society Press , 2001, p. 2043-2052, article id 925201Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we consider the mapping of two radar algorithms on a new scalable hardware architecture. The architecture consists of several computational modules that work independently and send data simultaneously in order to achieve high throughput. Each computational module is composed of multiple processors connected in a hypercube topology to meet scalability and high bisection bandwidth requirements. Free-space optical interconnects and planar packaging technology make it possible to transform the hypercubes into planes. Optical fan-out reduces the number of optical transmitters and thus the hardware cost. Two example systems are analyzed and mapped onto the architecture. One 64-channel airborne radar system with a sustained computational load of more than 1.6 TFLOPS, and one ground-based 128-channel radar system with extreme inter-processor communication demands.

Place, publisher, year, edition, pages
Los Alamitos, California: IEEE Computer Society Press, 2001
Keywords
optical interconnection networks
National Category
Computer Engineering
Identifiers
urn:nbn:se:hh:diva-2745 (URN)10.1109/IPDPS.2001.925201 (DOI)2-s2.0-84981285645 (Scopus ID)2082/3147 (Local ID)0-7695-0990-8 (ISBN)2082/3147 (Archive number)2082/3147 (OAI)
Conference
15th International Parallel and Distributed Processing Symposium, IPDPS 2001, San Francisco, United States, 23-27 April, 2001
Note

©2001 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

Available from: 2009-08-12 Created: 2009-08-12 Last updated: 2018-03-23Bibliographically approved
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