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Savas, S., Ul-Abdin, Z. & Nordström, T. (2019). A Configurable Two Dimensional Mesh Network-on-Chip Implementation in Chisel. In: : . Paper presented at 32nd IEEE International System-on-Chip Conference (SOCC), Singapore, September 3-6, 2019. IEEE conference proceedings
Open this publication in new window or tab >>A Configurable Two Dimensional Mesh Network-on-Chip Implementation in Chisel
2019 (English)Conference paper, Published paper (Refereed)
Abstract [en]

On-chip communication plays a significant role in the performance of manycore architectures. Therefore, they require a proper on-chip communication infrastructure that can scale with the number of the cores. As a solution, network-on-chip structures have emerged and are being used.

This paper presents description of a two dimensional mesh network-on-chip router and a network interface, which are implemented in Chisel to be integrated to the rocket chip generator that generates RISC-V (rocket) cores. The router is implemented in VHDL as well and the two implementations are verified and compared.

Hardware resource usage and performance of different sized networks are analyzed. The implementations are synthesized for a Xilinx Ultrascale FPGA via Xilinx tools for the hardware resource usage and clock frequency results. The performance results including latency and throughput measurements with different traffic patterns, are collected with cycle accurate emulations. 

The implementations in Chisel and VHDL do not show a significant difference. Chisel requires around 10% fewer lines of code, however, the difference in the synthesis results is negligible. Our latency result are better than the majority of the other studies. The other results such as hardware usage, clock frequency, and throughput are competitive when compared to the related works.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2019
Keywords
network-on-chip, Chisel, mesh, scalable
National Category
Computer Systems
Identifiers
urn:nbn:se:hh:diva-39324 (URN)
Conference
32nd IEEE International System-on-Chip Conference (SOCC), Singapore, September 3-6, 2019
Funder
Vinnova
Note

©2019 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

Available from: 2019-05-07 Created: 2019-05-07 Last updated: 2019-10-10
Savas, S., Ul-Abdin, Z. & Nordström, T. (2019). A Framework to Generate Domain-Specific Manycore Architectures from Dataflow Programs. Microprocessors and microsystems
Open this publication in new window or tab >>A Framework to Generate Domain-Specific Manycore Architectures from Dataflow Programs
2019 (English)In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436Article in journal (Refereed) Submitted
Abstract [en]

In the last 15 years we have seen, as a response to power and thermal limits for current chip technologies, an explosion in the use of multiple and even many computer cores on a single chip. But now, to further improve performance and energy efficiency, when there are potentially hundreds of computing cores on a chip, we see a need for a specialization of individual cores and the development of heterogeneous manycore computer architectures.

However, developing such heterogeneous architectures is a significant challenge. Therefore, we propose a design method to generate domain specific manycore architectures based on RISC-V instruction set architecture and automate the main steps of this method with software tools. The design method allows generation of manycore architectures with different configurations including core augmentation through instruction extensions and custom accelerators. The method starts from developing applications in a high-level dataflow language and ends by generating synthesizable Verilog code and cycle accurate emulator for the generated architecture.

We evaluate the design method and the software tools by generating several architectures specialized for two different applications and measure their performance and hardware resource usages. Our results show that the design method can be used to generate specialized manycore architectures targeting applications from different domains. The specialized architectures show at least 3 to 4 times better performance than the general purpose counterparts. In certain cases, replacing general purpose components with specialized components saves hardware resources. Automating the method increases the speed of architecture development and facilitates the design space exploration of manycore architectures.

Place, publisher, year, edition, pages
Amsterdam: Elsevier, 2019
Keywords
Domain-specific, multicore, manycore, accelerator, code generation, hardware/software co-design
National Category
Computer Systems Embedded Systems Signal Processing
Identifiers
urn:nbn:se:hh:diva-39323 (URN)
Funder
Vinnova
Available from: 2019-05-07 Created: 2019-05-07 Last updated: 2019-05-08
Savas, S., Yassin, A., Nordström, T. & Ul-Abdin, Z. (2019). Using Harmonized Parabolic Synthesis to Implement a Single-Precision Floating-Point Square Root Unit. In: : . Paper presented at International Symposium on VLSI Design (ISVLSI), Miami, Florida, USA, July 15-17, 2019. IEEE conference proceedings
Open this publication in new window or tab >>Using Harmonized Parabolic Synthesis to Implement a Single-Precision Floating-Point Square Root Unit
2019 (English)Conference paper, Published paper (Refereed)
Abstract [en]

This paper proposes a novel method for performing square root operation on floating-point numbers represented in IEEE-754 single-precision (binary32) format. The method is implemented using Harmonized Parabolic Synthesis. It is implemented with and without pipeline stages individually and synthesized for two different Xilinx FPGA boards.

The implementations show better resource usage and latency results when compared to other similar works including Xilinx intellectual property (IP) that uses the CORDIC method. Any method calculating the square root will make approximation errors. Unless these errors are distributed evenly around zero, they can accumulate and give a biased result. An attractive feature of the proposed method is the fact that it distributes the errors evenly around zero, in contrast to CORDIC for instance.

Due to the small size, low latency, high throughput, and good error properties, the presented floating-point square root unit is suitable for high performance embedded systems. It can be integrated into a processor’s floating point unit or be used as astand-alone accelerator.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2019
Keywords
square root, floating-point, harmonized parabolic synthesis, fpga, hardware
National Category
Embedded Systems Computer Systems
Identifiers
urn:nbn:se:hh:diva-39322 (URN)
Conference
International Symposium on VLSI Design (ISVLSI), Miami, Florida, USA, July 15-17, 2019
Funder
Vinnova
Available from: 2019-05-07 Created: 2019-05-07 Last updated: 2019-08-02
Savas, S., Ul-Abdin, Z. & Nordström, T. (2018). Designing Domain Specific Heterogeneous Manycore Architectures Based on Building Blocks.
Open this publication in new window or tab >>Designing Domain Specific Heterogeneous Manycore Architectures Based on Building Blocks
2018 (English)Manuscript (preprint) (Other academic)
Abstract [en]

Performance and power requirements has pushed computer architectures from single core to manycores. These requirements now continue pushing the manycores with identical cores (homogeneous) to manycores with specialized cores (heterogeneous). However designing heterogeneous manycores is a challenging task due to the complexity of the architectures. We propose an approach for designing domain specific heterogeneous manycore architectures based on building blocks. These blocks are defined as the common computations of the applications within a domain. The objective is to generate heterogeneous architectures by integrating many of these blocks to many simple cores and connect the cores with a networkon-chip. The proposed approach aims to ease the design of heterogeneous manycore architectures and facilitate usage of dark silicon concept. As a case study, we develop an accelerator based on several building blocks, integrate it to a RISC core and synthesize on a Xilinx Ultrascale FPGA. The results show that executing a hot-spot of an application on an accelerator based on building blocks increases the performance by 15x, with room for further improvement. The area usage increases as well, however there are potential optimizations to reduce the area usage. © 2018 by the authors

Keywords
heterogeneous architecture design, risc-v, dataflow, QR decomposition, domain-specific processor, accelerator, Autofocus, hardware software co-design
National Category
Embedded Systems
Identifiers
urn:nbn:se:hh:diva-33818 (URN)
Projects
HiPEC (High Performance Embedded Computing)NGES (Towards Next, Generation Embedded Systems: Utilizing Parallelism and Reconfigurability)
Funder
Swedish Foundation for Strategic Research VINNOVA
Available from: 2017-05-09 Created: 2017-05-09 Last updated: 2018-12-05Bibliographically approved
Savas, S., Ul-Abdin, Z. & Nordström, T. (2018). Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs. Computers, 7(2), Article ID 27.
Open this publication in new window or tab >>Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs
2018 (English)In: Computers, ISSN 2073-431X, Vol. 7, no 2, article id 27Article in journal (Refereed) Published
Abstract [en]

The last ten years have seen performance and power requirements pushing computer architectures using only a single core towards so-called manycore systems with hundreds of cores on a single chip. To further increase performance and energy efficiency, we are now seeing the development of heterogeneous architectures with specialized and accelerated cores. However, designing these heterogeneous systems is a challenging task due to their inherent complexity. We proposed an approach for designing domain-specific heterogeneous architectures based on instruction augmentation through the integration of hardware accelerators into simple cores. These hardware accelerators were determined based on their common use among applications within a certain domain.The objective was to generate heterogeneous architectures by integrating many of these accelerated cores and connecting them with a network-on-chip. The proposed approach aimed to ease the design of heterogeneous manycore architectures—and, consequently, exploration of the design space—by automating the design steps. To evaluate our approach, we enhanced our software tool chain with a tool that can generate accelerated cores from dataflow programs. This new tool chain was evaluated with the aid of two use cases: radar signal processing and mobile baseband processing. We could achieve an approximately 4x improvement in performance, while executing complete applications on the augmented cores with a small impact (2.5–13%) on area usage. The generated accelerators are competitive, achieving more than 90% of the performance of hand-written implementations.

Place, publisher, year, edition, pages
Basel: MDPI AG, 2018
Keywords
heterogeneous architecture design, risc-v, dataflow, QR decomposition, domain-specific processor, accelerator, Autofocus, hardware software co-design
National Category
Computer Systems
Identifiers
urn:nbn:se:hh:diva-36669 (URN)10.3390/computers7020027 (DOI)
Projects
Towards Next Generation Embedded Systems: Utilizing Parallelism and Reconfigurability (NGES)
Funder
Swedish Foundation for Strategic Research VINNOVA
Available from: 2018-04-24 Created: 2018-04-24 Last updated: 2019-05-07Bibliographically approved
Savas, S., Hertz, E., Nordström, T. & Ul-Abdin, Z. (2017). Efficient Single-Precision Floating-Point Division Using Harmonized Parabolic Synthesis. In: Michael Hübner, Ricardo Reis, Mircea Stan & Nikolaos Voros (Ed.), 2017 IEEE Computer Society Annual Symposium on VLSI: ISVLSI 2017. Paper presented at IEEE Computer Society Annual Symposium on VLSI, July 3-5, 2017, Bochum, Germany. Los Alamitos: IEEE
Open this publication in new window or tab >>Efficient Single-Precision Floating-Point Division Using Harmonized Parabolic Synthesis
2017 (English)In: 2017 IEEE Computer Society Annual Symposium on VLSI: ISVLSI 2017 / [ed] Michael Hübner, Ricardo Reis, Mircea Stan & Nikolaos Voros, Los Alamitos: IEEE, 2017Conference paper, Published paper (Refereed)
Abstract [en]

This paper proposes a novel method for performing division on floating-point numbers represented in IEEE-754 single-precision (binary32) format. The method is based on an inverter, implemented as a combination of Parabolic Synthesis and second-degree interpolation, followed by a multiplier. It is implemented with and without pipeline stages individually and synthesized while targeting a Xilinx Ultrascale FPGA.

The implementations show better resource usage and latency results when compared to other implementations based on different methods. In case of throughput, the proposed method outperforms most of the other works, however, some Altera FPGAs achieve higher clock rate due to the differences in the DSP slice multiplier design.

Due to the small size, low latency and high throughput, the presented floating-point division unit is suitable for high performance embedded systems and can be integrated into accelerators or be used as a stand-alone accelerator.

Place, publisher, year, edition, pages
Los Alamitos: IEEE, 2017
Series
IEEE Computer Society Annual Symposium on VLSI, ISSN 2159-3477
Keywords
Floating-point, single precision, division, FPGA, Harmonized Parabolic Synthesis
National Category
Computer Systems
Identifiers
urn:nbn:se:hh:diva-33793 (URN)10.1109/ISVLSI.2017.28 (DOI)2-s2.0-85027258772 (Scopus ID)978-1-5090-6762-6 (ISBN)978-1-5090-6763-3 (ISBN)
Conference
IEEE Computer Society Annual Symposium on VLSI, July 3-5, 2017, Bochum, Germany
Projects
NGES
Funder
VINNOVA
Available from: 2017-05-05 Created: 2017-05-05 Last updated: 2019-05-07Bibliographically approved
Kunert, K., Jonsson, M., Böhm, A. & Nordström, T. (2017). Providing Efficient Support for Real-Time Guarantees in a Fibre-Optic AWG-Based Network for Embedded Systems. Optical Switching and Networkning Journal, 24, 47-56
Open this publication in new window or tab >>Providing Efficient Support for Real-Time Guarantees in a Fibre-Optic AWG-Based Network for Embedded Systems
2017 (English)In: Optical Switching and Networkning Journal, ISSN 1573-4277, E-ISSN 1872-9770, Vol. 24, p. 47-56Article in journal (Refereed) Published
Abstract [en]

High-performance embedded systems running real-time applications demand communication solutions providing high data rates and low error probabilities, properties inherent to optical solutions. However, providing timing guarantees for deadline bound applications in this context is far from basic due to the parallelism inherent in multiwavelength networks and often bound to include a large amount of pessimism. Assuming deterministic medium access, an admission control algorithm using a schedulability analysis can ensure deadline guarantees for real-time communication. The traffic dependency analysis presented in this paper is specifically targeting a multichannel context, taking into consideration the possibility of concurrent transmissions in these types of networks. Combining our analysis with a feasibility analysis in admission control, the amount of guaranteed hard real-time traffic could be shown to increase by a factor 7 in a network designed for a radar signal processing case. Using this combination of analysis methods will render possible an increased amount of hard real-time traffic over a given multichannel network, leading to a more efficient bandwidth utilization by deadline dependent applications without having to redesign the network or the medium access method.

Place, publisher, year, edition, pages
Amsterdam: Elsevier, 2017
Keywords
Real-time communication, Embedded system, Worst-case analysis, Multiwavelength network, Arrayed waveguide grating
National Category
Communication Systems
Identifiers
urn:nbn:se:hh:diva-32469 (URN)10.1016/j.osn.2016.11.004 (DOI)000392776500006 ()2-s2.0-85006944209 (Scopus ID)
Available from: 2016-11-22 Created: 2016-11-22 Last updated: 2018-03-23Bibliographically approved
Savas, S., Raase, S., Gebrewahid, E., Ul-Abdin, Z. & Nordström, T. (2016). Dataflow Implementation of QR Decomposition on a Manycore. In: MES '16: Proceedings of the Third ACM International Workshop on Many-core Embedded Systems. Paper presented at MES '16, International Workshop on Many-core Embedded Systems, Seoul, Republic of Korea, June 19, 2016 (pp. 26-30). New York, NY: ACM Press
Open this publication in new window or tab >>Dataflow Implementation of QR Decomposition on a Manycore
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2016 (English)In: MES '16: Proceedings of the Third ACM International Workshop on Many-core Embedded Systems, New York, NY: ACM Press, 2016, p. 26-30Conference paper, Published paper (Refereed)
Abstract [en]

While parallel computer architectures have become mainstream, application development on them is still challenging. There is a need for new tools, languages and programming models. Additionally, there is a lack of knowledge about the performance of parallel approaches of basic but important operations, such as the QR decomposition of a matrix, on current commercial manycore architectures.

This paper evaluates a high level dataflow language (CAL), a source-to-source compiler (Cal2Many) and three QR decomposition algorithms (Givens Rotations, Householder and Gram-Schmidt). The algorithms are implemented both in CAL and hand-optimized C languages, executed on Adapteva's Epiphany manycore architecture and evaluated with respect to performance, scalability and development effort.

The performance of the CAL (generated C) implementations gets as good as 2\% slower than the hand-written versions. They require an average of 25\% fewer lines of source code without significantly increasing the binary size. Development effort is reduced and debugging is significantly simplified. The implementations executed on Epiphany cores outperform the GNU scientific library on the host ARM processor of the Parallella board by up to 30x. © 2016 Copyright held by the owner/author(s).

Place, publisher, year, edition, pages
New York, NY: ACM Press, 2016
National Category
Embedded Systems
Identifiers
urn:nbn:se:hh:diva-32371 (URN)10.1145/2934495.2934499 (DOI)2-s2.0-84991106778 (Scopus ID)978-1-4503-4262-9 (ISBN)
Conference
MES '16, International Workshop on Many-core Embedded Systems, Seoul, Republic of Korea, June 19, 2016
Projects
ESCHERHiPEC
Funder
Knowledge FoundationSwedish Foundation for Strategic Research ELLIIT - The Linköping‐Lund Initiative on IT and Mobile Communications
Available from: 2016-11-04 Created: 2016-11-04 Last updated: 2019-05-07Bibliographically approved
Sámano-Robles, R., Nordström, T., Santonja, S., Rom, W. & Tovar, E. (2016). The DEWI High-Level Architecture: Guidelines for Structuring Wireless Sensor Networks in Industrial Applications. In: 2016 Eleventh International Conference on Digital Information Management (ICDIM): . Paper presented at Eleventh International Conference on Digital Information Management (ICDIM 2016), Porto, Portugal, September 19-21, 2016 (pp. 274-280). New York: IEEE
Open this publication in new window or tab >>The DEWI High-Level Architecture: Guidelines for Structuring Wireless Sensor Networks in Industrial Applications
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2016 (English)In: 2016 Eleventh International Conference on Digital Information Management (ICDIM), New York: IEEE, 2016, p. 274-280Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents the high-level architecture (HLA) of the research project DEWI (dependable embedded wireless infrastructure). The objective of this HLA is to serve as a reference for the development of industrial wireless sensor and actuator networks (WSANs) based on the concept of the DEWI Bubble. The DEWI Bubble is defined here as a high-level abstraction of an industrial WSAN with enhanced interoperability (via standardized interfaces), technology reusability, and cross-domain development. This paper details the design criteria used to define the HLA and the organization of the infrastructure internal and external to the DEWI Bubble. The description includes the different perspectives, models or views of the architecture: the entity model, the layered model, and the functional view model (including an overview of interfaces). The HLA constitutes an extension of the ISO/IEC SNRA (sensor network reference architecture) towards the support of industrial applications. To improve interoperability with existing approaches the DEWI HLA also reuses some features from other standardized technologies and architectures. The HLA will allow networks with different industrial sensor technologies to exchange information between them or with external clients via standard interfaces, thus providing a consolidated access to sensor information of different domains. This is an important aspect for smart city applications, Big Data and internet-of-things (IoT). © Copyright 2016 IEEE

Place, publisher, year, edition, pages
New York: IEEE, 2016
Keywords
Wireless sensor networks, Logic gates, Wireless communication, Interoperability, Computer architecture, Actuators, Ad hoc networks
National Category
Communication Systems Embedded Systems Computer Engineering Computer Systems
Identifiers
urn:nbn:se:hh:diva-33217 (URN)10.1109/ICDIM.2016.7829797 (DOI)000398535200045 ()2-s2.0-85014395764 (Scopus ID)978-1-5090-2641-8 (ISBN)978-1-5090-2642-5 (ISBN)
Conference
Eleventh International Conference on Digital Information Management (ICDIM 2016), Porto, Portugal, September 19-21, 2016
Projects
DEWI
Note

Funded by FCT/MEC (Fundação para a Ciência e a Tecnologia), ERDF (European Regional Development Fund) under PT2020, CISTER Research Unit (CEC/04234), and by ARTEMIS/0004/2013-JU grant nr. 621353 (DEWI, www.dewi-project.eu)

Available from: 2017-02-06 Created: 2017-02-06 Last updated: 2018-01-13Bibliographically approved
Xypolitidis, B., Shabani, R., Khanderparkar, S. V., Ul-Abdin, Z., Savas, S. & Nordström, T. (2016). Towards Architectural Design Space Exploration for Heterogeneous Manycores. In: Yiannis Cotronis, Masoud Daneshtalab & George Angelos Papadopoulos (Ed.), Proceedings: 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processin: PDP 2016. Paper presented at 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP 2016), Heraklion, Crete, Greece, 17th-19th February, 2016 (pp. 805-810). Piscataway, NJ: IEEE Computer Society
Open this publication in new window or tab >>Towards Architectural Design Space Exploration for Heterogeneous Manycores
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2016 (English)In: Proceedings: 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processin: PDP 2016 / [ed] Yiannis Cotronis, Masoud Daneshtalab & George Angelos Papadopoulos, Piscataway, NJ: IEEE Computer Society, 2016, p. 805-810Conference paper, Published paper (Refereed)
Abstract [en]

Today many of the high performance embedded processors already contain multiple processor cores and we see heterogeneous manycore architectures being proposed. Therefore it is very desirable to have a fast way to explore various heterogeneous architectures through the use of an architectural design space exploration tool, giving the designer the option to explore design alternatives before the physical implementation. In this paper, we have extended Heracles, a design space exploration tool for (homogeneous) manycore architectures, to incorporate different types of processing cores, and thus allowus to model heterogeneity. Our tool, called the Heterogeneous Heracles System (HHS), can besides the already supported MIPS core also include OpenRISC cores. The new tool retains the possibility available in Heracles to perform register transfer level (RTL) simulations of each explored architecture in Verilog as well as synthesizing it to field-programmable gate arrays (FPGAs). To facilitate the exploration of heterogeneous architectures, we have also extended the graphical user interface (GUI) to support heterogeneity. This GUI provides options to configure the types of core, core settings, memory system and network topology. Some initial results on FPGA utilization are presented from synthesizing both homogeneous and heterogeneous manycore architectures, as well as some benchmark results from both simulated and synthesized architectures.

Place, publisher, year, edition, pages
Piscataway, NJ: IEEE Computer Society, 2016
Keywords
Heterogeneous manycores, Heterogeneous Heracles, OpenRISC, Manycore architectures, Design Space Exploration
National Category
Computer Systems
Identifiers
urn:nbn:se:hh:diva-30394 (URN)10.1109/PDP.2016.79 (DOI)000381810900121 ()2-s2.0-849688208552-s2.0-84968820855 (Scopus ID)978-1-4673-8775-0 (ISBN)
Conference
24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP 2016), Heraklion, Crete, Greece, 17th-19th February, 2016
Projects
ESCHERHiPEC
Funder
Knowledge FoundationSwedish Foundation for Strategic Research
Available from: 2016-02-23 Created: 2016-02-23 Last updated: 2017-11-30Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0002-0562-2082

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