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Savas, S., Ul-Abdin, Z. & Nordström, T. (2019). A Configurable Two Dimensional Mesh Network-on-Chip Implementation in Chisel. In: : . Paper presented at 32nd IEEE International System-on-Chip Conference (SOCC), Singapore, September 3-6, 2019. IEEE conference proceedings
Open this publication in new window or tab >>A Configurable Two Dimensional Mesh Network-on-Chip Implementation in Chisel
2019 (English)Conference paper, Published paper (Refereed)
Abstract [en]

On-chip communication plays a significant role in the performance of manycore architectures. Therefore, they require a proper on-chip communication infrastructure that can scale with the number of the cores. As a solution, network-on-chip structures have emerged and are being used.

This paper presents description of a two dimensional mesh network-on-chip router and a network interface, which are implemented in Chisel to be integrated to the rocket chip generator that generates RISC-V (rocket) cores. The router is implemented in VHDL as well and the two implementations are verified and compared.

Hardware resource usage and performance of different sized networks are analyzed. The implementations are synthesized for a Xilinx Ultrascale FPGA via Xilinx tools for the hardware resource usage and clock frequency results. The performance results including latency and throughput measurements with different traffic patterns, are collected with cycle accurate emulations. 

The implementations in Chisel and VHDL do not show a significant difference. Chisel requires around 10% fewer lines of code, however, the difference in the synthesis results is negligible. Our latency result are better than the majority of the other studies. The other results such as hardware usage, clock frequency, and throughput are competitive when compared to the related works.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2019
Keywords
network-on-chip, Chisel, mesh, scalable
National Category
Computer Systems
Identifiers
urn:nbn:se:hh:diva-39324 (URN)
Conference
32nd IEEE International System-on-Chip Conference (SOCC), Singapore, September 3-6, 2019
Funder
Vinnova
Note

©2019 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

Available from: 2019-05-07 Created: 2019-05-07 Last updated: 2019-10-10
Savas, S., Ul-Abdin, Z. & Nordström, T. (2019). A Framework to Generate Domain-Specific Manycore Architectures from Dataflow Programs. Microprocessors and microsystems
Open this publication in new window or tab >>A Framework to Generate Domain-Specific Manycore Architectures from Dataflow Programs
2019 (English)In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436Article in journal (Refereed) In press
Abstract [en]

In the last 15 years we have seen, as a response to power and thermal limits for current chip technologies, an explosion in the use of multiple and even many computer cores on a single chip. But now, to further improve performance and energy efficiency, when there are potentially hundreds of computing cores on a chip, we see a need for a specialization of individual cores and the development of heterogeneous manycore computer architectures.

However, developing such heterogeneous architectures is a significant challenge. Therefore, we propose a design method to generate domain specific manycore architectures based on RISC-V instruction set architecture and automate the main steps of this method with software tools. The design method allows generation of manycore architectures with different configurations including core augmentation through instruction extensions and custom accelerators. The method starts from developing applications in a high-level dataflow language and ends by generating synthesizable Verilog code and cycle accurate emulator for the generated architecture.

We evaluate the design method and the software tools by generating several architectures specialized for two different applications and measure their performance and hardware resource usages. Our results show that the design method can be used to generate specialized manycore architectures targeting applications from different domains. The specialized architectures show at least 3 to 4 times better performance than the general purpose counterparts. In certain cases, replacing general purpose components with specialized components saves hardware resources. Automating the method increases the speed of architecture development and facilitates the design space exploration of manycore architectures.

Place, publisher, year, edition, pages
Amsterdam: Elsevier, 2019
Keywords
Domain-specific, multicore, manycore, accelerator, code generation, hardware/software co-design
National Category
Computer Systems Embedded Systems Signal Processing
Identifiers
urn:nbn:se:hh:diva-39323 (URN)10.1016/j.micpro.2019.102908 (DOI)
Funder
Vinnova
Available from: 2019-05-07 Created: 2019-05-07 Last updated: 2019-10-23
Savas, S., Yassin, A., Nordström, T. & Ul-Abdin, Z. (2019). Using Harmonized Parabolic Synthesis to Implement a Single-Precision Floating-Point Square Root Unit. In: : . Paper presented at International Symposium on VLSI Design (ISVLSI), Miami, Florida, USA, July 15-17, 2019. IEEE conference proceedings
Open this publication in new window or tab >>Using Harmonized Parabolic Synthesis to Implement a Single-Precision Floating-Point Square Root Unit
2019 (English)Conference paper, Published paper (Refereed)
Abstract [en]

This paper proposes a novel method for performing square root operation on floating-point numbers represented in IEEE-754 single-precision (binary32) format. The method is implemented using Harmonized Parabolic Synthesis. It is implemented with and without pipeline stages individually and synthesized for two different Xilinx FPGA boards.

The implementations show better resource usage and latency results when compared to other similar works including Xilinx intellectual property (IP) that uses the CORDIC method. Any method calculating the square root will make approximation errors. Unless these errors are distributed evenly around zero, they can accumulate and give a biased result. An attractive feature of the proposed method is the fact that it distributes the errors evenly around zero, in contrast to CORDIC for instance.

Due to the small size, low latency, high throughput, and good error properties, the presented floating-point square root unit is suitable for high performance embedded systems. It can be integrated into a processor’s floating point unit or be used as astand-alone accelerator.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2019
Keywords
square root, floating-point, harmonized parabolic synthesis, fpga, hardware
National Category
Embedded Systems
Identifiers
urn:nbn:se:hh:diva-39322 (URN)
Conference
International Symposium on VLSI Design (ISVLSI), Miami, Florida, USA, July 15-17, 2019
Funder
Vinnova
Available from: 2019-05-07 Created: 2019-05-07 Last updated: 2019-10-14
Savas, S., Ul-Abdin, Z. & Nordström, T. (2018). Designing Domain Specific Heterogeneous Manycore Architectures Based on Building Blocks.
Open this publication in new window or tab >>Designing Domain Specific Heterogeneous Manycore Architectures Based on Building Blocks
2018 (English)Manuscript (preprint) (Other academic)
Abstract [en]

Performance and power requirements has pushed computer architectures from single core to manycores. These requirements now continue pushing the manycores with identical cores (homogeneous) to manycores with specialized cores (heterogeneous). However designing heterogeneous manycores is a challenging task due to the complexity of the architectures. We propose an approach for designing domain specific heterogeneous manycore architectures based on building blocks. These blocks are defined as the common computations of the applications within a domain. The objective is to generate heterogeneous architectures by integrating many of these blocks to many simple cores and connect the cores with a networkon-chip. The proposed approach aims to ease the design of heterogeneous manycore architectures and facilitate usage of dark silicon concept. As a case study, we develop an accelerator based on several building blocks, integrate it to a RISC core and synthesize on a Xilinx Ultrascale FPGA. The results show that executing a hot-spot of an application on an accelerator based on building blocks increases the performance by 15x, with room for further improvement. The area usage increases as well, however there are potential optimizations to reduce the area usage. © 2018 by the authors

Keywords
heterogeneous architecture design, risc-v, dataflow, QR decomposition, domain-specific processor, accelerator, Autofocus, hardware software co-design
National Category
Embedded Systems
Identifiers
urn:nbn:se:hh:diva-33818 (URN)
Projects
HiPEC (High Performance Embedded Computing)NGES (Towards Next, Generation Embedded Systems: Utilizing Parallelism and Reconfigurability)
Funder
Swedish Foundation for Strategic Research VINNOVA
Available from: 2017-05-09 Created: 2017-05-09 Last updated: 2018-12-05Bibliographically approved
Savas, S., Ul-Abdin, Z. & Nordström, T. (2018). Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs. Computers, 7(2), Article ID 27.
Open this publication in new window or tab >>Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs
2018 (English)In: Computers, ISSN 2073-431X, Vol. 7, no 2, article id 27Article in journal (Refereed) Published
Abstract [en]

The last ten years have seen performance and power requirements pushing computer architectures using only a single core towards so-called manycore systems with hundreds of cores on a single chip. To further increase performance and energy efficiency, we are now seeing the development of heterogeneous architectures with specialized and accelerated cores. However, designing these heterogeneous systems is a challenging task due to their inherent complexity. We proposed an approach for designing domain-specific heterogeneous architectures based on instruction augmentation through the integration of hardware accelerators into simple cores. These hardware accelerators were determined based on their common use among applications within a certain domain.The objective was to generate heterogeneous architectures by integrating many of these accelerated cores and connecting them with a network-on-chip. The proposed approach aimed to ease the design of heterogeneous manycore architectures—and, consequently, exploration of the design space—by automating the design steps. To evaluate our approach, we enhanced our software tool chain with a tool that can generate accelerated cores from dataflow programs. This new tool chain was evaluated with the aid of two use cases: radar signal processing and mobile baseband processing. We could achieve an approximately 4x improvement in performance, while executing complete applications on the augmented cores with a small impact (2.5–13%) on area usage. The generated accelerators are competitive, achieving more than 90% of the performance of hand-written implementations.

Place, publisher, year, edition, pages
Basel: MDPI AG, 2018
Keywords
heterogeneous architecture design, risc-v, dataflow, QR decomposition, domain-specific processor, accelerator, Autofocus, hardware software co-design
National Category
Computer Systems
Identifiers
urn:nbn:se:hh:diva-36669 (URN)10.3390/computers7020027 (DOI)
Projects
Towards Next Generation Embedded Systems: Utilizing Parallelism and Reconfigurability (NGES)
Funder
Swedish Foundation for Strategic Research VINNOVA
Available from: 2018-04-24 Created: 2018-04-24 Last updated: 2019-05-07Bibliographically approved
Rezk, N., Purnaprajna, M. & Ul-Abdin, Z. (2018). Streaming Tiles: Flexible Implementation of Convolution Neural Networks Inference on Manycore Architectures. In: 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW): . Paper presented at The 7th International Workshop on Parallel and Distributed Computing for Large Scale Machine Learning and Big Data Analytics, Vancouver, British Columbia, Canada, May 21, 2018 (pp. 867-876). Los Alamitos: IEEE Computer Society
Open this publication in new window or tab >>Streaming Tiles: Flexible Implementation of Convolution Neural Networks Inference on Manycore Architectures
2018 (English)In: 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Los Alamitos: IEEE Computer Society, 2018, p. 867-876Conference paper, Published paper (Refereed)
Abstract [en]

Convolution neural networks (CNN) are extensively used for deep learning applications such as image recognition and computer vision. The convolution module of these networks is highly compute-intensive. Having an efficient implementation of the convolution module enables realizing the inference part of the neural network on embedded platforms. Low precision parameters require less memory, less computation time, and less power consumption while achieving high classification accuracy. Furthermore, streaming the data over parallelized processing units saves a considerable amount of memory, which is a key concern in memory constrained embedded platforms. In this paper, we explore the design space for streamed CNN on Epiphany manycore architecture using varying precisions for weights (ranging from binary to 32-bit). Both AlexNet and GoogleNet are explored for two different memory sizes of Epiphany cores. We are able to achieve competitive performance for both Alexnet and GoogleNet with respect to emerging manycores. Furthermore, the effects of different design choices in terms of precision, memory size, and the number of cores are evaluated by applying the proposed method.

Place, publisher, year, edition, pages
Los Alamitos: IEEE Computer Society, 2018
Keywords
manycores, CNN, stream processing, embedded systems
National Category
Embedded Systems
Identifiers
urn:nbn:se:hh:diva-36887 (URN)10.1109/IPDPSW.2018.00138 (DOI)978-1-5386-5555-9 (ISBN)978-1-5386-5556-6 (ISBN)
Conference
The 7th International Workshop on Parallel and Distributed Computing for Large Scale Machine Learning and Big Data Analytics, Vancouver, British Columbia, Canada, May 21, 2018
Projects
NGES (Towards Next Generation Embedded Systems: Utilizing Parallelism and Reconfigurability)
Funder
VINNOVA
Note

Funding: VINNOVA Strategic Innovation grant and the Department of Science and Technology, Government of India. ©2018 IEEE

Available from: 2018-06-01 Created: 2018-06-01 Last updated: 2018-08-20Bibliographically approved
Ul-Abdin, Z. & Mingkun, Y. (2017). A Radar Signal Processing Case Study for Dataflow Programming of Manycores. Journal of Signal Processing Systems, 87(1), 49-62
Open this publication in new window or tab >>A Radar Signal Processing Case Study for Dataflow Programming of Manycores
2017 (English)In: Journal of Signal Processing Systems, ISSN 1939-8018, E-ISSN 1939-8115, Vol. 87, no 1, p. 49-62Article in journal (Refereed) Published
Abstract [en]

The successful realization of next generation radar systems have high performance demands on the signal processing chain. Among these are advanced Active Electronically Scanned Array (AESA) radars in which complex calculations are to be performed on huge sets of data in real-time. Manycore architectures are designed to provide flexibility and high performance essential for such streaming applications. This paper deals with the implementation of compute-intensive parts of AESA radar signal processing chain in a high-level dataflow language; CAL. We evaluate the approach by targeting a commercial manycore architecture, Epiphany, and present our findings in terms of performance and productivity gains achieved in this case study. The comparison of the performance results with the reference sequential implementations executing on a state-of-the-art embedded processor show that we are able to achieve a speedup of 1.6x to 4.4x by using only 10 cores of Epiphany. © Springer Science+Business Media New York 2015

Place, publisher, year, edition, pages
New York: Springer-Verlag New York, 2017
Keywords
Dataflow language, Manycore architecture, Radar signal processing, Compiler
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:hh:diva-29826 (URN)10.1007/s11265-015-1078-1 (DOI)000396155700004 ()2-s2.0-84948408530 (Scopus ID)
Projects
STAMPHiPEC
Funder
Knowledge FoundationELLIIT - The Linköping‐Lund Initiative on IT and Mobile CommunicationsSwedish Foundation for Strategic Research
Available from: 2015-11-26 Created: 2015-11-26 Last updated: 2017-11-29Bibliographically approved
Gebrewahid, E. & Ul-Abdin, Z. (2017). Actor Fission Transformations for Executing Dataflow Programs on Manycores. In: 2017 Forum on Specification and Design Languages (FDL): . Paper presented at FDL 2017 - Forum on specification & Design Languages, Verona, Italy, September 18-20, 2017.
Open this publication in new window or tab >>Actor Fission Transformations for Executing Dataflow Programs on Manycores
2017 (English)In: 2017 Forum on Specification and Design Languages (FDL), 2017Conference paper, Published paper (Other academic)
Abstract [en]

Manycore architectures are dominating the development of advanced embedded computing due to the computational and power demand of high performance applications. This has introduced an additional complexity with regard to the efficient exploitation of the underlying hardware and the development of efficient parallel implementations. To tackle this we model applications using a dataflow programming language, perform high-level transformations of dataflow actors, and generate native code by using our compilation framework.This paper presents the actor fission transformations of our Cal2Many compilation framework. The transformations have facilitated the mapping of big dataflow actors on memory restricted embedded manycores, increased the utilization of the hardware, and enabled support for task and data-level parallelism. We have applied the actor transformations to two blocks of MPEG-4 decoder and executed it on the Epiphany manycore architecture. The result shows the practicality and feasibility of our approach.

Keywords
Dataflow Languages, Manycores, Compiler, Embedded systems, MPEG-4 decoder
National Category
Embedded Systems
Identifiers
urn:nbn:se:hh:diva-34881 (URN)10.1109/FDL.2017.8303891 (DOI)978-1-5386-4733-2 (ISBN)978-1-5386-1152-4 (ISBN)
Conference
FDL 2017 - Forum on specification & Design Languages, Verona, Italy, September 18-20, 2017
Available from: 2017-09-05 Created: 2017-09-05 Last updated: 2018-03-13Bibliographically approved
Gebrewahid, E., Ul-Abdin, Z. & Gaspes, V. (2017). Cal2Many: A Framework to Compile Dataflow Programs for Manycores.
Open this publication in new window or tab >>Cal2Many: A Framework to Compile Dataflow Programs for Manycores
2017 (English)Manuscript (preprint) (Other academic)
Abstract [en]

The arrival of manycore platforms has imposed programming challenges for mainstream embedded system developers. In this paper, we discuss the significance of actor-oriented dataflow languages and present our compilation framework for CAL Actor Language that leads to increased portability and retargetability. We demonstrate the applicability of our approach with streaming applications targeting the Epiphany many-core architecture. We have performed an in-depth analysis of MPEG-4 SP implemented on Epiphany using our framework and studied the effects of actor composition. We have identified hardware aspects such as increased off-chip memory bandwidth and larger local memories that could result in further performance improvements.

Keywords
Design, Algorithms, Performance, dataflow languages, compilation framework, manycore, CAL
National Category
Embedded Systems
Identifiers
urn:nbn:se:hh:diva-34882 (URN)
Available from: 2017-09-05 Created: 2017-09-05 Last updated: 2017-12-06Bibliographically approved
Savas, S., Hertz, E., Nordström, T. & Ul-Abdin, Z. (2017). Efficient Single-Precision Floating-Point Division Using Harmonized Parabolic Synthesis. In: Michael Hübner, Ricardo Reis, Mircea Stan & Nikolaos Voros (Ed.), 2017 IEEE Computer Society Annual Symposium on VLSI: ISVLSI 2017. Paper presented at IEEE Computer Society Annual Symposium on VLSI, July 3-5, 2017, Bochum, Germany. Los Alamitos: IEEE
Open this publication in new window or tab >>Efficient Single-Precision Floating-Point Division Using Harmonized Parabolic Synthesis
2017 (English)In: 2017 IEEE Computer Society Annual Symposium on VLSI: ISVLSI 2017 / [ed] Michael Hübner, Ricardo Reis, Mircea Stan & Nikolaos Voros, Los Alamitos: IEEE, 2017Conference paper, Published paper (Refereed)
Abstract [en]

This paper proposes a novel method for performing division on floating-point numbers represented in IEEE-754 single-precision (binary32) format. The method is based on an inverter, implemented as a combination of Parabolic Synthesis and second-degree interpolation, followed by a multiplier. It is implemented with and without pipeline stages individually and synthesized while targeting a Xilinx Ultrascale FPGA.

The implementations show better resource usage and latency results when compared to other implementations based on different methods. In case of throughput, the proposed method outperforms most of the other works, however, some Altera FPGAs achieve higher clock rate due to the differences in the DSP slice multiplier design.

Due to the small size, low latency and high throughput, the presented floating-point division unit is suitable for high performance embedded systems and can be integrated into accelerators or be used as a stand-alone accelerator.

Place, publisher, year, edition, pages
Los Alamitos: IEEE, 2017
Series
IEEE Computer Society Annual Symposium on VLSI, ISSN 2159-3477
Keywords
Floating-point, single precision, division, FPGA, Harmonized Parabolic Synthesis
National Category
Computer Systems
Identifiers
urn:nbn:se:hh:diva-33793 (URN)10.1109/ISVLSI.2017.28 (DOI)2-s2.0-85027258772 (Scopus ID)978-1-5090-6762-6 (ISBN)978-1-5090-6763-3 (ISBN)
Conference
IEEE Computer Society Annual Symposium on VLSI, July 3-5, 2017, Bochum, Germany
Projects
NGES
Funder
VINNOVA
Available from: 2017-05-05 Created: 2017-05-05 Last updated: 2019-05-07Bibliographically approved
Projects
Towards Next Generation Embedded Systems: Utilizing Parallelism and Reconfigurability [2015-04178_Vinnova]; Halmstad University; Publications
Savas, S., Ul-Abdin, Z. & Nordström, T. (2019). A Configurable Two Dimensional Mesh Network-on-Chip Implementation in Chisel. In: : . Paper presented at 32nd IEEE International System-on-Chip Conference (SOCC), Singapore, September 3-6, 2019. IEEE conference proceedingsSavas, S., Ul-Abdin, Z. & Nordström, T. (2019). A Framework to Generate Domain-Specific Manycore Architectures from Dataflow Programs. Microprocessors and microsystemsSavas, S. (2019). Hardware/Software Co-Design of Heterogeneous Manycore Architectures. (Doctoral dissertation). Halmstad: Halmstad University PressSavas, S., Yassin, A., Nordström, T. & Ul-Abdin, Z. (2019). Using Harmonized Parabolic Synthesis to Implement a Single-Precision Floating-Point Square Root Unit. In: : . Paper presented at International Symposium on VLSI Design (ISVLSI), Miami, Florida, USA, July 15-17, 2019. IEEE conference proceedings
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0002-4932-4036

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